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Patent # Description
US-9,735,952 Calibration of dynamic error in high resolution digital-to-time converters
A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction...
US-9,735,894 High performance receiver architecture and methods thereof
A user equipment (UE), receiver and method are generally described herein. The UE may include a mixer, a local oscillator (LO) and an analog-to-digital...
US-9,735,893 Patch system for in-situ therapeutic treatment
Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy...
US-9,735,819 Mobile communications radio receiver for multiple network operation
A radio receiver for multiple radio network operation includes an RF unit for generating a first down-converted signal from a radio signal received from a first...
US-9,735,813 Method and apparatus for signal edge boosting
Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a...
US-9,735,812 Digital RF receiver power saving with signal quality dependent word length reduction
A radio frequency (RF) transceiver system comprises an input port configured to receive an RF receive signal and a receiver (RX) digital signal processing (DSP)...
US-9,735,765 Apparatuses, methods, and systems for jitter equalization and phase error detection
Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a...
US-9,735,747 Balancing mobile device audio
Techniques related to balancing audio for mobile devices are discussed. Such techniques may include detecting a speaker of the device is at least partially...
US-9,735,412 Rechargeable battery and method to suppress dendrite
A battery cell includes a first current collector, a cathode in electrical contact with the first current collector, and a second current collector. The second...
US-9,735,348 High stability spintronic memory
An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed...
US-9,735,120 Low z-height package assembly
In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die...
US-9,735,089 Thermal management for flexible integrated circuit packages
Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may...
US-9,734,988 Exposure apparatus and exposure method
To form a complex and fine pattern by combining optical exposure technology and charged particle beam exposure technology, provided is an exposure apparatus...
US-9,734,880 Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions
Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit...
US-9,734,866 Perceptual computing input to determine post-production effects
Systems, apparatuses and methods may provide for detecting an event in visual content including one or more of a video or a still image and searching an effects...
US-9,734,691 Personalized wearable gas sensor using both the average and the rate of change of the gas level
Embodiments of a system and method for determining a personalized gas level exposure are generally described herein. A method may include receiving, at a...
US-9,734,597 Interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing...
A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices....
US-9,734,531 Determining a profile for a recommendation engine based on group interaction dynamics
A technique includes using a processor-based machine to determine a dynamic interaction characteristic of a group of users. The technique further includes,...
US-9,734,359 Always-available embedded theft reaction subsystem
A system to provide an always-on embedded anti-theft protection for a platform is described. The system comprises in one embodiment, a storage including...
US-9,734,263 Method and apparatus for efficient pre-silicon debug
Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification...
US-9,734,116 Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is...
US-9,734,079 Hybrid exclusive multi-level memory architecture with memory management
Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller...
US-9,734,077 Sending packets using optimized PIO write sequences without sfences
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to...
US-9,734,069 Multicast tree-based data distribution in distributed shared cache
Systems and methods for multicast tree-based data distribution in a distributed shared cache. An example processing system comprises: a plurality of processing...
US-9,734,054 Efficient implementation of geometric series
Methods and apparatus related to efficient implementation of geometric series are discussed herein. For example, memory stores data corresponding to a geometric...
US-9,733,995 Scalable synchronization mechanism for distributed memory
A method comprising receiving control information at a first processing element from a second processing element, synchronizing objects within a shared global...
US-9,733,987 Techniques to dynamically allocate resources of configurable computing resources
Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of...
US-9,733,956 Adjusting settings based on sensor data
Various techniques for adjusting settings based on sensor data are described herein. In one example, a method includes detecting sensor data from a sensor and...
US-9,733,944 Instruction sequence buffer to store branches having reliably predictable instruction sequences
A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit...
US-9,733,942 Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to...
US-9,733,939 Physical reference list for tracking physical register sharing
A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical...
US-9,733,937 Compare and exchange operation using sleep-wakeup mechanism
A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an...
US-9,733,935 Super multiply add (super madd) instruction
A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first...
US-9,733,913 Methods and systems to vectorize scalar computer program loops having loop-carried dependences
Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method...
US-9,733,909 System converter that implements a reordering process through JIT (just in time) optimization that ensures...
A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter...
US-9,733,858 Supporting data compression using match scoring
A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a...
US-9,733,689 Hardware apparatuses and methods to perform transactional power management
Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a...
US-9,733,363 Filtering for global positioning system (GPS) receivers
Devices and methods are directed to estimating a position of the device/user using a delta range measurement (DRM) module to measure a range difference between...
US-9,733,282 Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator
Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic...
US-9,730,120 Handover using group evolved packet system (EPS) bearers
Technology for a target evolved node B (eNB) operable to facilitate handover is disclosed. The target eNB can receive a handover request message to hand over a...
US-9,730,102 Methods and arrangements for packet flows in wireless networks
Logic may compress wireless communications frames and communicate compressed frames that do not include the duplicative bit sequences within the packet flow....
US-9,729,849 3D video coding including depth based disparity vector calibration
Systems, apparatus, articles, and methods are described including operations for 3D video coding including depth based disparity vector calibration.
US-9,728,995 Systems, methods and devices for adaptable battery charging
Because a rechargeable battery has an increased number of uses (e.g., cycles), the battery's internal impedance can increase and the efficiency of the battery...
US-9,728,464 Self-aligned 3-D epitaxial structures for MOS device fabrication
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within...
US-9,728,425 Space-efficient underfilling techniques for electronic assemblies
Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting...
US-9,727,345 Method for booting a heterogeneous system and presenting a symmetric core view
A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set...
US-9,727,267 Power management and monitoring for storage devices
In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the...
US-9,723,646 LTE+CDMA 1x hybrid
An apparatus for communicating over a circuit switched network and a packetized data network. The apparatus includes a packetized data modem, a circuit switched...
US-9,723,547 Mechanisms for roaming between 3GPP operators and WLAN service providers
Embodiments describe methods, apparatuses and logic for a user equipment (UE) to connect to an access point (AP) in a wireless local area network (WLAN) based...
US-9,723,508 Wireless interference mitigation
A User Equipment and an eNodeB system are configured for performing interference mitigation in the UE. Input circuitry in the wireless communication device...
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