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Patent # Description
US-1,025,6881 Apparatus, system and method of sounding feedback sequence of explicit beamforming training
Some demonstrative embodiments include devices, systems and/or methods of simultaneously communicating with a group of wireless communication devices. For...
US-1,025,6878 Method, wireless device, and computer readable medium for conducting a multiple station beam refinement...
New wireless networks can perform enhanced beamforming training for a multiple access technique, such as orthogonal frequency division multiple-access (OFDMA)....
US-1,025,6876 Quantized eigen beams for controlling antenna array elements in a wireless network
An apparatus of a wireless communication device operable to communicate channel state information in a wireless network can include memory and processing...
US-1,025,6842 Technologies for correcting flipped bits for an error correction decode process
Technologies for correcting flipped bits prior to performing an error correction decode process include an apparatus that includes a memory to store a redundant...
US-1,025,6761 Monitoring health of electrical equipment
Techniques for monitoring the health of a device comprising a motor or generator are described. An apparatus to monitor the health of the device includes a...
US-1,025,6665 Power transmitting device having wire-free power transfer safety detection
An electronic device may include a power driver to receive power and to selectively provide power, and a plurality of power transfer contacts to receive power...
US-1,025,6656 Device control for wireless charging
A system and method may be used for controlling a device charging on a wireless charger. A method may include disabling, in response to determining that the...
US-1,025,6521 Waveguide connector with slot launcher
The systems and methods described herein provide a traveling wave launcher system physically and communicably coupled to a semiconductor package and to a...
US-1,025,6395 Capped magnetic memory
An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between...
US-1,025,6286 Integrated inductor for integrated circuit devices
A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or...
US-1,025,6219 Forming embedded circuit elements in semiconductor package assembles and structures formed thereby
Methods of forming stacked die assemblies are described. Those methods/structures may include forming a circuit element on a first substrate, wherein a first...
US-1,025,6213 Reduced-height electronic memory system and method
A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the...
US-1,025,6211 Multi-chip-module semiconductor chip package having dense package wiring
An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The...
US-1,025,6208 Overlapping stacked die package with vertical columns
Some forms relate to an electronic assembly (10) that includes a die (11) that includes an upper surface (12) and a conductive column (13) extending from the...
US-1,025,6206 Qubit die attachment using preforms
Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary...
US-1,025,6205 Variable ball height on ball grid array packages by solder paste transfer
BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold...
US-1,025,6198 Warpage control for microelectronics packages
Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a...
US-1,025,6141 Maskless air gap to prevent via punch through
A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an...
US-1,025,6074 Exposure apparatus and exposure method
To form a complex and fine pattern by combining optical exposure technology and charged particle beam exposure technology, provided is an exposure apparatus...
US-1,025,5911 System and method of automatic speech recognition using parallel processing for weighted finite state...
A computer-implemented method of speech recognition comprises forming a weighted finite state transducer (WFST) having nodes associated with states and...
US-1,025,5909 Statistical-analysis-based reset of recurrent neural networks for automatic speech recognition
Techniques are provided for calculating reset parameters for recurrent neural networks (RNN). A methodology implementing the techniques according to an...
US-1,025,5771 Apparatus and methods for haptic covert communication
Embodiments described herein relate generally to providing information through tactility. A computer system may receive an input from a user. The computer...
US-1,025,5656 Compute optimization mechanism
An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit...
US-1,025,5654 Facilitating dynamic parallel scheduling of command packets at graphics processing units on computing devices
A mechanism is described for facilitating parallel scheduling of multiple commands on computing devices. A method of embodiments, as described herein, includes...
US-1,025,5425 Secure authentication protocol systems and methods
An input device of a secure authentication protocol system may receive at least one user authentication factor in a pre-boot session. The input device may...
US-1,025,5399 Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect
In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path...
US-1,025,5305 Technologies for object-based data consistency in distributed architectures
Technologies for object-based data consistency in a fabric architecture includes a network switch communicatively coupled to a plurality of computing nodes. The...
US-1,025,5203 Technologies for zero-copy inter-virtual-machine data movement
Technologies for zero-copy inter-virtual-machine communication include a computing device with extended page table support. A sender virtual machine stores data...
US-1,025,5202 Multi-tenant encryption for storage class memory
Various embodiments are generally directed to the providing for mutual authentication and secure distributed processing of multi-party data. In particular, an...
US-1,025,5199 Evicting clean secure pages without encryption
Secure memory paging technologies are described. Embodiments of the disclosure may include checking attributes of secure page cache map to determine whether a...
US-1,025,5196 Method and apparatus for sub-page write protection
An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a...
US-1,025,5187 Systems and methods for implementing weak stream software data and instruction prefetching using a hardware...
A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software...
US-1,025,5144 Decoding device and method using context redundancy
The disclosure relates to a decoding device, comprising: a receiver configured to provide a sequence of information bits comprising context redundancy...
US-1,025,5126 Aggregated page fault signaling and handling
A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The...
US-1,025,5122 Function callback mechanism between a Central Processing Unit (CPU) and an auxiliary processor
Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor...
US-1,025,5109 High bandwidth connection between processor dies
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially...
US-1,025,5093 Techniques for portable computing device virtualization
Various embodiments are generally directed to providing virtualization using relatively minimal processing and storage resources to enable concurrent isolated...
US-1,025,5077 Apparatus and method for a hybrid latency-throughput processor
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For...
US-1,025,5076 Method for performing dual dispatch of blocks and half blocks
A method by a processor for performing multi-dispatch of instruction blocks. The method includes receiving an incoming sequence of instructions, grouping the...
US-1,025,5072 Architectural register replacement for instructions that use multiple architectural registers
A processor of an aspect includes a decode unit to decode an instruction. The instruction is to explicitly specify a first architectural register and is to...
US-1,025,4979 Relocating or aborting a block of data by a host, based on media policies managed by a storage device
A storage device transmits a message to a host, where the message indicates that at an opportune time the host should relocate or abort a block of data that is...
US-1,025,4977 Achieving consistent read times in multi-level non-volatile memory
Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level...
US-1,025,4919 One-click tagging user interface
Methods and systems may provide for identifying a first user selection of one or more objects in an interface, and determining a tag associated with a second...
US-1,025,4854 Tracker for cursor navigation
A system for a tracker for cursor navigation is described herein. The system includes a display, camera, memory, and processor. The memory that is to store...
US-1,025,4845 Hand gesture recognition for cursor control
A system for hand gesture recognition is described herein. The system includes a display, camera, memory, and processor. The memory that is to store...
US-1,025,4821 Managing surprise hot plug in low power state
An apparatus is provided which comprises: an input/output (I/O) port; a first circuitry to update an in-band presence detect field, based on communication via...
US-1,025,4818 Priority based application event control (PAEC) to reduce power consumption
Methods and apparatus relating to Based Priority Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may...
US-1,025,4763 Detection of traffic dynamics and road changes in autonomous driving
In some embodiments, the disclosed subject matter involves a system and method for dynamic object identification and environmental changes for use with...
US-1,025,4744 Telerobotic controller
Various systems and methods for controlling a robot are described herein.
US-1,025,4178 Ambient temperature estimation
Techniques for estimating ambient temperature are described herein. Temperature data may be received from a first sensor of a computing device. Temperature data...
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