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Patent # Description
US-8,058,710 Interconnects having sealing structures to enable selective metal capping layers
Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an...
US-8,058,690 Integration of planar and tri-gate devices on the same substrate
An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain;...
US-8,058,177 Winged vias to increase overlay margin
Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer...
US-8,057,108 Method and apparatus to generate and monitor optical signals and control power levels thereof in a planar...
Embodiments of an optical detection apparatus are disclosed which may include one or more of a waveguide, a trench formed in the waveguide, a reflective...
US-8,056,221 Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery
An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more...
US-8,055,914 Voltage regulation for a computer system providing voltage positioning for multi-component load
A computer system has a controller and a voltage regulator. The controller generates a power consumption state signal for one or more components of the computer...
US-8,055,851 Line swapping scheme to reduce back invalidations in a snoop filter
In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors,...
US-8,055,805 Opportunistic improvement of MMIO request handling based on target reporting of space requirements
Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space...
US-8,055,697 Method and device for dynamically verifying a processor architecture
A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least...
US-8,054,921 Mitigating noise created by spread spectrum clocks
A platform to mitigate noise caused by spread spectrum clock signals. The platform may comprise a noise mitigation block, which may include a first set of...
US-8,054,875 Autoregressive moving average modeling for feedforward and feedback Tomlinson-Harashima precoder filters
Apparatus and methods provide a Tomlinson-Harashima precoder scheme in which a feedback filter may be constructed to match an approximated feedforward filter,...
US-8,054,629 Microfins for cooling an ultramobile device
The present invention discloses a method of cooling an ultramobile device with microfins attached to an external wall of an enclosure surrounding the...
US-8,053,774 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode...
US-8,051,458 System and method for dynamic channel management of a television based on media center set-top box tuner...
A method and system for dynamic channel management of a television based on media center set-top box tuner availability. The method includes determining a last...
US-8,051,448 Method and apparatus for displaying entertainment system data upon selection of a video data display
A graphical user interface (GUI) includes a first window that displays video data of a first entertainment selection. A first area of the first window displays...
US-8,051,355 Multilevel low density parity-check coded modulation
A method and apparatus are provided for encoding and decoding a communication signal. Processes for encoding and decoding the communication signal use a first...
US-8,051,314 Serial ATA (SATA) power optimization through automatic deeper power state transition
A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial...
US-8,051,232 Data storage device performance optimization methods and apparatuses
Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed....
US-8,050,454 Processing digital video using trajectory extraction and spatiotemporal decomposition
Methods to process digital video using trajectory extraction and spatiotemporal decomposition for search and retrieval of video are described. An example method...
US-8,050,204 Concentric rings wireless network architecture
A wireless network includes access points arranged in concentric rings and grids of concentric rings. At low network loads, only access points in the center are...
US-8,050,177 Interconnect bandwidth throttler
An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of...
US-8,050,116 Memory cell write
Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module...
US-8,046,576 Offloading the processing of a network protocol stack
A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to...
US-8,046,559 Memory rank burst scheduling
A method, device, and system are disclosed. In one embodiment the method includes grouping multiple memory requests into multiple of memory rank queues. Each...
US-8,046,539 Method and apparatus for the synchronization of distributed caches
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to...
US-8,046,516 Cache coherent switch device
In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of...
US-8,046,488 Dynamically modulating link width
Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding...
US-8,046,024 Multi-radio platform with WiMax and bluetooth radio modules and method
Embodiments of a multi-radio platform with longer-range and shorter-range radio modules and method are generally described herein. Other embodiments may be...
US-8,045,992 Uplink and downlink control signaling in wireless networks
Embodiments of the present invention provide for downlink and uplink control feedback signaling. In some embodiments, one or more bits indicating a validation...
US-8,045,666 Spread spectrum clock generator
Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.
US-8,045,449 OFDM receiver and methods for operating in high-throughput and increased range modes
An OFDM receiver operates in a high-throughput mode or an increased-range mode. The receiver includes FFT circuitry to generate frequency domain ...
US-8,044,957 Subdividing geometry images in graphics hardware
A system may include a graphics memory, a data bus, a processor, and a vertex shader. The data bus may be operatively connected to the graphics memory. The...
US-8,044,773 Parallel RFID system using CDMA
Various embodiments of the invention may use code division multiple access (CDMA) technology in communications from radio frequency identification (RFID) tags...
US-8,044,697 Per die temperature programming for thermally efficient integrated circuit (IC) operation
Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments,...
US-8,044,497 Stacked die package
The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a...
US-8,044,431 Microdisplay packaging system
Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled...
US-8,044,305 Circuit board including hybrid via structures
A circuit board may include hybrid via structures configured to connect to components, such as connectors and electronic components, mounted on the circuit...
US-8,042,190 Pre-boot protected memory channel
Machine readable media, methods, and computing devices are disclosed which establish a protected memory channel between an operating system loader of a user...
US-8,042,109 Framework for domain-specific run-time environment acceleration using virtualization technology
In some embodiments, the invention involves a framework for using virtualization technology to efficiently support a domain-specific run-time environment. In at...
US-8,042,025 Determining a message residue
In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect,...
US-8,041,951 Code-based communication connection management
In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the...
US-8,041,945 Method and apparatus for performing an authentication after cipher operation in a network processor
A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing...
US-8,041,934 Transmission distinguishing apparatus, systems, and methods
Apparatus and systems, as well as methods and articles, may operate to distinguish between sources of signals transmitted with a pilot carrier based upon a...
US-8,041,932 Method and apparatus for assigning devices to a partition
Devices in a processing system may be managed by performing a first scan of a bus of the processing system from a first partition. In one embodiment, the first...
US-8,041,920 Partitioning memory mapped device configuration space
Embodiments of apparatuses, methods, and systems for partitioning memory mapped device configuration space are disclosed. In one embodiment, an apparatus...
US-8,041,898 Method, system and apparatus for reducing memory traffic in a distributed memory system
The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a...
US-8,041,857 Dynamic A-MSDU enabling
A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to...
US-8,041,854 Steering data units to a consumer
A computer system may comprise a second device operating as a producer that may steer data units to a first device operating as a consumer. A processing core of...
US-8,041,844 Autodetection of a PCI express device operating at a wireless RF mitigation frequency
A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits...
US-8,041,794 Platform discovery, asset inventory, configuration, and provisioning in a pre-boot environment using web services
In one embodiment, the present invention includes a method for initializing a common information model (CIM) broker and a SLP service agent of a system in a...
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