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Patent # Description
US-9,210,009 Digital pre-distortion filter system and method
A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude...
US-9,210,006 Method for processing a data signal and receiver circuit
A method includes receiving a signal including a co-channel interference, channel equalizing the received signal and processing the channel equalized signal...
US-9,209,958 Segmented digital-to-time converter calibration
This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a...
US-9,209,872 MU-MIMO access point and user station including methods for multi-user group management
Embodiments of a MU-MIMO access point, user station and method for multi-user group management are generally described herein. In some embodiments, a MU-MIMO...
US-9,209,821 Apparatus for generating quadrature clock phases from a single-ended odd-stage ring oscillator
Described is an apparatus which comprises: a ring oscillator having odd number of delay stages; and an interpolator to receive at least three phases from the...
US-9,209,820 Apparatus for symmetric and linear time-to-digital converter (TDC)
Described is a linear and symmetric time-to-digital converter (TDC) which comprises: a first input; a second input; a first delay line having a plurality of...
US-9,209,604 Hybrid laser including anti-resonant waveguides
Described are embodiments of apparatuses and systems including a hybrid laser including anti-resonant waveguides, and methods for making such apparatuses and...
US-9,209,369 Edge coupling alignment using embedded features
Methods and systems may provide an alignment scheme for components that may reduce positional deviation between the components. The method may include placing a...
US-9,209,290 III-N material structure for gate-recessed transistors
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the...
US-9,209,288 Reduced scale resonant tunneling field effect transistor
An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major...
US-9,209,199 Stacked thin channels for boost and leakage improvement
A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar...
US-9,209,143 Die edge side connection
An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the...
US-9,209,136 Hybrid carbon-metal interconnect structures
Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit...
US-9,209,077 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an...
US-9,208,888 Techniques for improving reliability and performance of partially written memory blocks in modern flash memory...
Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a...
US-9,208,881 NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch....
US-9,208,860 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual...
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in...
US-9,208,853 Dual-port static random access memory (SRAM)
In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access...
US-9,208,602 Techniques and architecture for improved vertex processing
An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache...
US-9,208,575 Method and device for detecting face, and non-transitory computer-readable recording medium for executing the...
In the present disclosure, a plurality of frames of input images sequentially received for a predetermined time interval is obtained, and a face detecting...
US-9,208,375 Face recognition mechanism
The present disclosure relates to a face recognition method, an apparatus, and a computer-readable recording medium for executing the method. According to some...
US-9,208,359 Always-available embedded theft reaction subsystem
A platform including an always-available theft protection system is described. In one embodiment, the system comprises a power management logic to selectively...
US-9,208,354 Techniques for securing use of one-time passwords
Various embodiments are generally directed to the provision and use of a secure enclave defined within a storage of a computing device by a processor element...
US-9,208,302 Multi-factor authentication using biometric data
Technologies for enabling biometric multi-factor authentication includes a transform selector value, a transform function that uses the transform selector value...
US-9,208,299 Secure user authentication with improved one-time-passcode verification
Generally, this disclosure provides systems, devices, methods and computer readable media for secure user authentication with improved OTP verification. The...
US-9,208,292 Entering a secured computing environment using multiple authenticated code modules
Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a...
US-9,208,124 Reset of processing core in multi-core processing system
This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core...
US-9,208,121 High performance interconnect physical layer
A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical...
US-9,208,110 Raw memory transaction support
Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring...
US-9,208,022 Techniques for adaptive moving read references for memory cell read error recovery
Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage...
US-9,207,994 Scheduling tasks among processor cores
Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described...
US-9,207,988 Method, system, and device for managing server hardware resources in a cloud scheduling environment
A method, system, and device for managing hardware resources in a cloud scheduling environment includes a zone controller. The zone controller can manage groups...
US-9,207,945 Multi-persona computing based on real time user recognition
A computing device may configure one or more applications on the computing device for a specific user in response to identifying that the specific user is...
US-9,207,942 Systems, apparatuses,and methods for zeroing of bits in a data element
Embodiments of systems, methods and apparatuses for execution a NAME instruction are described. The execution of a VPBZHI causes, on a per data element basis of...
US-9,207,941 Systems, apparatuses, and methods for reducing the number of short integer multiplications
Systems, methods, and apparatuses for calculating a square of a data value of a first source operand, a square of a data value of a second source operand, and a...
US-9,207,940 Robust and high performance instructions for system call
Robust system call and system return instructions are executed by a processor to transfer control between a requester and an operating system kernel. The...
US-9,207,910 Digital signal processor having instruction set with an x.sup.K function using reduced look-up table
A digital signal processor is provided having an instruction set with an x.sup.K function that uses a reduced look-up table. The disclosed digital signal...
US-9,207,880 Processor with architecturally-visible programmable on-die storage to store data that is accessible by instruction
A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access...
US-9,207,753 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry...
Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline...
US-9,207,750 Apparatus and method for reducing leakage power of a circuit
Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled...
US-9,207,749 Mechanism for facilitating efficient operations paths for storage devices in computing systems
A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A...
US-9,207,274 Direct liquid-contact micro-channel heat transfer devices, methods of temperature control for semiconductive...
An apparatus to test a semiconductive device includes a base plane that holds at least one heat-transfer fluid unit cell. The at least one heat-transfer fluid...
US-9,207,258 Composite wire probes for testing integrated circuits
An electrical probe of an aspect includes a high yield strength wire core. The high yield strength wire core includes predominantly one or more materials...
US-9,206,523 Nanomachined structures for porous electrochemical capacitors
Embodiments of the invention describe energy storage devices, porous electrodes, and methods of formation. In an embodiment, an energy storage device includes a...
US-9,205,744 PC-based automobile owner's manual, diagnostics, and auto care
A computer built into an automobile displays the owner's manual for the car. The user requests more information about the automobile through the computer, and...
US-9,205,340 Stowable expanding controller for a mobile gaming device, apparatus and system
Embodiments of an apparatus, system and method are described for mobile gaming. In some embodiments an apparatus comprises one or more processors and an...
US-9,204,814 Hand-held heart monitor
A heart monitor is provided herein. The heart monitor includes a housing and first and second electrodes disposed in a first surface of the housing. At least a...
US-9,204,489 Method, apparatus and system of communication over multiple frequency bands
Devices, systems and methods of communication over multiple wireless communication frequency bands. For example, a multiple frequency band (multi-band) wireless...
US-9,204,459 LTE operation in white spaces
One embodiment of the present invention relates to a method for efficient reassignment of a secondary communication channel (having a first priority) within a...
US-9,204,446 Collaborative radio resources allocations to applications of mobile units
Collecting state information about the resources of radio access networks (RANs) and the Access Point Names (APNs) enables this information to be provided to...
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