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Patent # Description
US-1,002,1814 Cooling apparatus for computer memory
Embodiments herein relate to liquid cooling interfaces for computer memory components. An apparatus for cooling a computer memory component may include a...
US-1,002,1743 Light devices having controllable light emitting elements
In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching...
US-1,002,1716 Method for solving conflicts in scheduling cell broadcast message reception and idle mode tasks of a mobile device
A method (200) for solving conflicts in scheduling cell broadcast (CB) message reception and idle mode tasks of a mobile device includes: receiving (201) first...
US-1,002,1705 Carrier measurements for multi-carrier devices
Technology for a user equipment (UE) operable to perform carrier measurements in a wireless network is disclosed. The UE can receive, from a network element,...
US-1,002,1628 Preventing a mobile device from repeating a request toward a mobile network
Briefly, in accordance with one or more embodiments, a network node of a first Public Land Mobile Network (PLMN) receives a request from a user equipment (UE)...
US-1,002,1595 Aggregation procedures for a media access control layer
A radio communication device includes a wireless transmission circuit and a control processing circuit adapted to interact with the wireless transmission...
US-1,002,1586 Pushing back packet not acknowledged by base station
An apparatus for reducing latency in a User Equipment (UE), comprising a processor configured to push back a packet that is transmitted to but not acknowledged...
US-1,002,1556 Automatic seamless context sharing across multiple devices
Embodiments of a system and method for automatic context sharing across multiple devices are generally described herein. In some embodiments, an application...
US-1,002,1408 Video codec and motion estimation method
The invention provides a video codec. In one embodiment, the video codec is coupled to an outer memory storing a reference frame, and comprises an interface...
US-1,002,1392 Content adaptive bi-directional or functionally predictive multi-pass pictures for high efficiency next...
Techniques related to content adaptive bi-directional or functionally predictive multi-pass pictures for high efficiency next generation video coding.
US-1,002,1387 Performance and bandwidth efficient fractional motion estimation
Described herein are techniques related to motion estimation for video encoding. In particular, integer estimation is performed on a reference video frame, and...
US-1,002,1382 Calibrating a one-dimensional coded light 3D acquisition system
A camera intrinsic calibration may be performed using an object geometry. An intrinsic camera matrix may then be recovered. A homography is fit between object...
US-1,002,1346 Interactive video conferencing
Technology for a local user equipment (UE) operable to perform video conferencing with a remote UE is disclosed. The local UE can receive a set of predefined...
US-1,002,0967 PAM-n jitter/noise decomposition analysis
A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes...
US-1,002,0934 Hardware accelerator for cryptographic hash operations
In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of...
US-1,002,0931 Apparatus for dynamically adapting a clock generator with respect to changes in power supply
Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in...
US-1,002,0837 Transmit leakage cancellation in a wide bandwidth distributed antenna system
A system and methods for cancelling transmission leakage signals in a wide bandwidth Distributed Antenna System ("DAS") having remote units is disclosed. An...
US-1,002,0816 Hybrid successive approximation register analog to digital converter
Systems, methods, and circuitries for converting an analog voltage to a digital signal are provided. In one example a method to convert an analog voltage into a...
US-1,002,0812 Techniques for variable latency redundancy
An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the...
US-1,002,0684 Apparatus, system and method of multiple device wireless power transfer
Some demonstrative embodiments include apparatuses, systems and/or methods of wireless power transfer. For example, an apparatus may include a wireless power...
US-1,002,0665 Power delivery system
An electronic apparatus may include a charger device to obtain information relating to a first battery, and to set a limit of a battery charge current of a...
US-1,002,0375 Tungsten gates for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate...
US-1,002,0371 Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one...
US-1,002,0313 Antifuse with backfilled terminals
An antifuse may include a non-planar conductive terminal having a high-z portion extending to a greater z-height than a low-z portion. A second conductive...
US-1,002,0262 High resolution solder resist material for silicon bridge application
In accordance with disclosed embodiments, there are provided high resolution solder resist material for silicon bridge application. For instance, in accordance...
US-1,002,0232 Integrated circuits with recessed gate electrodes
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
US-1,002,0037 Capacity register file
An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each...
US-1,001,9836 Planar depth representations for block compression
Described herein are technologies related to facilitate high precision and resolution of a depth (Z) buffer storage during a process of rendering 3D scenes....
US-1,001,9825 Karaoke avatar animation based on facial motion data
Apparatus, systems, media and/or methods may involve animating avatars. User facial motion data may be extracted that corresponds to one or more user facial...
US-1,001,9722 Poll-based networking system
Described is a poll-based system that provides an on-line network of products, goods and services that are determined through polling each of the users. This...
US-1,001,9662 System and method for electronically tagging items for use in controlling electrical devices
A system and method for electronically tagging items for use in controlling electrical devices are disclosed. A particular embodiment includes: a controller; a...
US-1,001,9644 Technologies for determining local differentiating color for image feature detectors
Technologies for multi-channel feature detection include a computing device to determine a filter response of each image channel of a multi-channel image for...
US-1,001,9601 Method and apparatus for securely saving and restoring the state of a computing platform
An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data...
US-1,001,9574 Systems and methods for providing dynamic file system awareness on storage devices
Systems and methods for providing awareness of a host file system on a storage device are described. In one embodiment, a storage device includes a host...
US-1,001,9400 Additional secured execution environment with SR-IOV and xHCI-IOV
An apparatus is described herein. The apparatus includes a Universal Serial Bus (USB) component and a controller interface. The controller interface is to...
US-1,001,9390 Using memory cache for a race free interrupt scheme without the use of "read clear" registers
A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a...
US-1,001,9385 Method and apparatus of real-time retimer delay measurement
Described is an apparatus comprising a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may be an elastic...
US-1,001,9366 Satisfying memory ordering requirements between partial reads and non-snoop accesses
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein...
US-1,001,9360 Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data...
Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer...
US-1,001,9354 Apparatus and method for fast cache flushing including determining whether data is to be stored in nonvolatile...
Apparatus, systems, and methods to manage memory operations are described. A cache controller is provided comprising logic to receive a transaction to operate...
US-1,001,9342 Data flow programming of computing apparatus with vector estimation-based graph partitioning
In various embodiments, a spectral graph partitioner ("SP") of a graph partitioning system ("GPS") may partition a data flow graph associated with a program...
US-1,001,9341 Using hardware performance counters to detect stale memory objects
Systems and methods may provide for conducting an object trace of an allocation status of one or more objects in a computing system and using one or more...
US-1,001,9300 Live error recovery
A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is...
US-1,001,9280 Technologies for dynamically managing data bus bandwidth usage of virtual machines in a network device
Technologies for dynamically managing data bus bandwidth usage of virtual machines include a network device that includes a data bus, one or more processors...
US-1,001,9273 Virtual environment manager
A virtual environment manager ("VEM") simplifies the usability of virtual machines and provides users with an enhanced design for creating and/or for managing...
US-1,001,9264 System and method for contextual vectorization of instructions at runtime
Methods and apparatuses relating to processors that contextually optimize instructions at runtime are disclosed. In one embodiment, a processors includes a...
US-1,001,9263 Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
In a processor, a disambiguation-free out of order load store queue method. The method includes implementing a memory resource that can be accessed by a...
US-1,001,9262 Vector store/load instructions for array of structures
A processor comprises a plurality of vector registers, and an execution unit, operatively coupled to the plurality of vector registers, the execution unit...
US-1,001,9198 Method and apparatus for processing sequential writes to portions of an addressable unit
Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of...
US-1,001,9071 Gesture pre-processing of video stream using a markered region
Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive...
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