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Patent # Description
US-8,193,641 Recessed workfunction metal in CMOS transistor gates
A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the...
US-8,193,593 Multi-layer gate dielectric
A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second...
US-8,193,567 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable...
US-8,193,523 Germanium-based quantum well devices
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close...
US-8,193,072 Semiconductor wafer coat layers and methods therefor
Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat...
US-8,193,049 Methods of channel stress engineering and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion...
US-8,191,793 Method and system of advanced fan speed control
According to some embodiments, a method, system, and apparatus to provide thermal management control. In some embodiments, the method includes receiving, by a...
US-8,191,062 System for processor frequency governors to govern a processor frequency by deriving CPU utilization...
A method, apparatus and system enable processor frequency governors to comprehend virtualized platforms. Specifically, in one embodiment, the processor...
US-8,190,930 Methods and apparatuses for controlling thread contention
An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first...
US-8,190,870 Network storage target boot and network connectivity through a common network device
The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network...
US-8,190,867 Packing two packed signed data in registers with saturation
A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers,...
US-8,190,863 Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction
A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource...
US-8,190,859 Critical section detection and prediction mechanism for hardware lock elision
A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock...
US-8,190,845 System and method for allocating and deallocating memory within transactional code
Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods...
US-8,190,841 Method of managing sectors of a non-volatile memory
Machine-readable media, methods, apparatus and system for managing sectors of a non-volatile memory are described. In some embodiments, a plurality of file...
US-8,190,830 Method, apparatus, and systems to support execution pipelining in a memory controller
A memory controller may execute instructions instead of sending the instructions to a processor for execution. To maintain synchronization between the memory...
US-8,190,820 Optimizing concurrent accesses in a directory-based coherency protocol
In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to...
US-8,190,778 Method and apparatus for network filtering and firewall protection on a secure partition
A management virtual machine on a virtualization technology enabled platform includes a means for providing a firewall and deep packet inspection. An isolated...
US-8,190,770 Segmentation and reassembly of data frames
A system and method of transmitting data frames between a plurality of input ports to a plurality of output ports is described. The input ports segment portions...
US-8,190,765 Data reception management apparatus, systems, and methods
Computer network apparatus may include a packet-receiving module to receive a packet into an element of a storage array while a low resource state exists, an...
US-8,190,652 Achieving coherence between dynamically optimized code and original code
Techniques for achieving coherence between dynamically optimized code and original code are disclosed. In an embodiment, a search is performed for a first entry...
US-8,190,168 Enhanced scheduling techniques for wireless communication networks
An enhanced beamforming with interference nulling method is an improvement over prior art beamforming with interference nulling techniques. The enhanced method...
US-8,190,167 Wireless device channel selection using dynamic channel allocation
Embodiments of methods and apparatus for dynamic channel allocation are disclosed. In various embodiments, an access point (AP) of an infrastructure based...
US-8,190,152 Wireless network roaming timer method and apparatus
A mobile station in a wireless network includes a roaming timer. The roaming timer is set based on various criteria, and when the roaming timer expires, an...
US-8,190,111 Two-point polar modulator and method for generating a polar-modulated signal based on amplitude information and...
A two-point polar modulator for generating a polar-modulated signal based on an amplitude information and a phase information includes a two-point modulation...
US-8,190,091 Method for setting data transmission parameters and communication device
A method for setting data transmission parameters of a first communication connection comprising determining information about data transmission parameters of...
US-8,189,792 Method and apparatus for performing cryptographic operations
In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round...
US-8,189,710 Architecture and methods for coexistence of wireless radios having differing protocols
Embodiments of systems and methods for the coexistence of wireless radios having differing protocols are generally described herein. Other embodiments may be...
US-8,189,705 Method and apparatus to perform equalization and decoding for a communication system
A method and apparatus to perform equalization and decoding for a communication system are described. The embodiments may be directed to a method and apparatus...
US-8,189,694 Transmitting and receiving arrangement with a channel-oriented link
A transmitting and receiving arrangement as well as a method for transmission of monitoring and/or payload data in a transmitting and receiving arrangement for...
US-8,189,619 Systems and methods facilitating high throughput control in wireless communications
Embodiments include systems and methods for frame tunneling in a wireless communications system comprising digital beam forming. Embodiments comprise a first...
US-8,189,573 Method and apparatus for configuring at least one port in a switch to be an upstream port or a downstream port
A method and apparatus are described herein for configuring at least one port in a switch to be an upstream port or a downstream port based, at least in part,...
US-8,189,361 Multi-chip assembly with optically coupled die
Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of...
US-8,189,343 Method and apparatus to provide power to a backplane
Embodiments are generally direct to a method and apparatus to provide power to a backplane. In one embodiment, a method is implemented in a backplane to receive...
US-8,189,119 Channel control techniques
Techniques involving the reception of content are disclosed. For example, an apparatus may include a tuning detection module, a channel selection module, and a...
US-8,188,594 Input/output package architectures
A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an...
US-8,186,231 Method and apparatus for scanning a textile
Some embodiments disclosed herein provide novel approaches for rapidly sensing sense line cross-point interaction in a textile such as a carpet or rug. A...
US-8,186,051 Method for fabricating package substrate and die spacer layers having a ceramic backbone
Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated...
US-8,185,886 Method and apparatus to enable dynamically activated firmware updates
Dynamic updating of firmware in a processing system without performing a system reset may be accomplished by allocating memory space for updated firmware in a...
US-8,185,758 Method and system for determining an energy-efficient operating point of a platform
A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of...
US-8,185,734 System and method for execution of a secured environment initialization instruction
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates...
US-8,185,723 Method and apparatus to extract integer and fractional components from floating-point data
A method is presented including decomposing a first value into many parts. Decomposing includes shifting (310) a rounded integer portion of the first value to...
US-8,185,700 Enabling speculative state information in a cache coherency protocol
In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a...
US-8,185,671 Technique for increasing control and status signal density in a fixed register address space
A plurality of registers may function as both the control and status registers. Each bit location of the registers is writable to set a value on a control...
US-8,185,571 Processor for performing multiply-add operations on packed data
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is...
US-8,185,398 Reading device with shortcut read function
In some embodiments, a reading device is provided with a shortcut read mode in which a user can instruct the reading device of the type of document (e.g.,...
US-8,185,102 Reducing co-interference on a multi-radio platform
A wireless communications device in a first network with contention-based access may send a special frame to one or more other devices in the first network,...
US-8,185,072 Method and apparatus for power reduction for interconnect links
A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver....
US-8,185,063 Impedance matched transmitting arrangement
A transmitting arrangement includes a matching circuit, a reference circuit and a comparator. The output of the matching circuit can be coupled to an antenna...
US-8,184,855 Three-level scheme for efficient ball tracking
A three-level ball detection and tracking method is disclosed. The ball detection and tracking method employs three levels to generate multiple ball candidates...
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