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| Patent # | Description |
|---|---|
| US-9,414,309 |
Mobile terminal A mobile terminal is provided comprising a component to be supplied with power having a power input terminal, a radio receiver configured to receive... |
| US-9,414,306 |
Device-to-device (D2D) preamble design This application discusses, among other things, methods and apparatus for providing more efficient ways to enable D2D discovery and D2D communication... |
| US-9,414,304 |
Method and related mobile device for cell searching with low memory
requirement The present solution relates to a method for searching for a cell in a cellular mobile communication system having low memory requirement. The method comprises:... |
| US-9,414,125 |
Remote control device An apparatus may include a housing that has a substantially equiaxed shape. The apparatus may include a motion sensor that detects a rotational state of the... |
| US-9,413,765 |
Multinode hubs for trusted computing Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a... |
| US-9,413,583 |
Calibrating RF path delay and IQ phase imbalance for polar transmit system A method of calibrating parameters for a polar transmitter (Polar TX) system includes receiving phase information derived from transmission information in a... |
| US-9,413,446 |
Method, apparatus and communication unit A method, an apparatus and a communication unit for generating precoding feedback information in a multiple frequency radio transmission system are disclosed. A... |
| US-9,413,434 |
Cancellation of interfering audio on a mobile device Generally, this disclosure provides devices, systems and methods for cancelling an interfering audio signal. The system may include a mobile device including a... |
| US-9,413,402 |
Dynamic low IF injection side selection A low IF receiver for operation at an intermediate frequency (IF), comprises an antenna port configured to receive a receive signal comprising a wanted RF... |
| US-9,413,365 |
Oscillator with controllable frequency Apparatuses are disclosed which comprise a coarse tuning circuitry, a fine tuning circuitry and at least one switchable capacitance. |
| US-9,413,364 |
Apparatus and method for clock synchronization for inter-die synchronized
data transfer Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an... |
| US-9,413,326 |
Second-order filter with notch for use in receivers to effectively
suppress the transmitter blockers The disclosed invention relates to a transceiver system comprising a notch filter element configured to suppress transmitter blockers (i.e., transmitter... |
| US-9,413,299 |
Systems and methods utilizing adaptive envelope tracking A communication system utilizing adaptive envelope tracking includes a transmit path, a feedback receiver, a parameter component and an envelope tracking... |
| US-9,413,097 |
High density cabled midplanes and backplanes A cabled midplane includes a first support plate along a plane between a first connector set and a second connector set that connect to line cards on either... |
| US-9,413,079 |
Single-package phased array module with interleaved sub-arrays Embodiments of the present disclosure are directed to a single-package communications device that includes an antenna module with a plurality of independently... |
| US-9,412,872 |
N-type and P-type tunneling field effect transistors (TFETs) Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling... |
| US-9,412,860 |
Multi-layer gate dielectric A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second... |
| US-9,412,821 |
Stacked thin channels for boost and leakage improvement A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar... |
| US-9,412,702 |
Laser die backside film removal for integrated circuit (IC) packaging Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die... |
| US-9,412,625 |
Molded insulator in package assembly Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material.... |
| US-9,412,195 |
Constant buffer size multi-sampled anti-aliasing depth compression By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples,... |
| US-9,412,002 |
Wearable electronic device having a fingerprint identification display Particular embodiments described herein provide for a wearable electronic device, such as a bracelet, watch, wristband or armband that includes a circuit board... |
| US-9,411,983 |
Apparatus and method to protect digital content In an embodiment of the present invention, a processor includes content storage logic to parse digital content into portions and to cause each portion to be... |
| US-9,411,975 |
Methods and apparatus to securely share data Methods and apparatus to securely share data are disclosed. An example includes generating, at a first device of a first user of cloud services, an archive file... |
| US-9,411,946 |
Fingerprint password Various systems and methods for authenticating a user are described herein. A system to includes a biometric scanner to scan an input sequence of biometric... |
| US-9,411,775 |
iWARP send with immediate data operations Apparatus, methods and systems for supporting Send with Immediate Data messages using Remote Direct Memory Access (RDMA) and the Internet Wide Area RDMA... |
| US-9,411,763 |
Allocation of flow control credits for high performance devices Methods and apparatus relating to allocation of flow control credits for high performance devices are described. In some embodiments, controls and/or... |
| US-9,411,762 |
Method and system for platform management messages across peripheral
component interconnect express (PCIe) segments A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root... |
| US-9,411,748 |
Secure replay protected storage Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such... |
| US-9,411,739 |
System, method and apparatus for improving transactional memory (TM)
throughput using TM region indicators Systems, apparatuses, and methods for improving transactional memory (TM) throughput using a TM region indicator (or color) are described. Through the use of TM... |
| US-9,411,728 |
Methods and apparatus for efficient communication between caches in
hierarchical caching design In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient... |
| US-9,411,725 |
Application-reserved cache for direct I/O Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache... |
| US-9,411,724 |
Method and apparatus for a partial-address select-signal generator with
address shift In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a... |
| US-9,411,714 |
Finite state machine for system management Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic.... |
| US-9,411,683 |
Error correction in memory Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction... |
| US-9,411,667 |
Recovery after input/ouput error-containment events Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a... |
| US-9,411,651 |
RDMA (remote direct memory access) data transfer in a virtual environment In an embodiment, a method is provided. In an embodiment, the method provides determining that a message has been placed in a send buffer; and transferring the... |
| US-9,411,601 |
Flexible bootstrap code architecture The present disclosure is directed to flexible bootstrap code architecture. A device may comprise equipment for operating the device and an operating system... |
| US-9,411,600 |
Instructions and logic to provide memory access key protection
functionality Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A... |
| US-9,411,593 |
Processors, methods, systems, and instructions to consolidate unmasked
elements of operation masks An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an... |
| US-9,411,592 |
Vector address conflict resolution with vector population count
functionality Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register... |
| US-9,411,586 |
Apparatus and method for an instruction that determines whether a value is
within a range A method is described that includes performing the following with a single instruction: receiving a first input operand V; receiving a second input operand S;... |
| US-9,411,584 |
Methods, apparatus, instructions, and logic to provide vector address
conflict detection functionality Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of... |
| US-9,411,583 |
Vector instruction for presenting complex conjugates of respective complex
numbers An apparatus is described having a semiconductor chip that has an instruction execution pipeline. The instruction execution pipeline has an execution unit with... |
| US-9,411,405 |
Method for reducing power consumption in solid-state storage device Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD,... |
| US-9,411,398 |
Electronic device and method to extend battery life An electronic apparatus is provided that includes a processor, a voltage regulator, a battery controller and an embedded controller. The voltage regulator to... |
| US-9,411,395 |
Method and apparatus to control current transients in a processor In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP... |
| US-9,411,363 |
Synchronization in a computing device One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more... |
| US-9,409,767 |
Energy storage structure, method of manufacturing a support structure for
same, and microelectronic assembly... An energy storage structure includes an energy storage device containing at least one porous structure (110, 120, 510, 1010) that contains multiple channels... |
| US-9,408,216 |
Dynamic bandwidth allocation to transmit a wireless protocol across a
code division multiple access (CDMA)... A technique for transmission of wireless signals across CDMA radio links. Bandwidth is allocated dynamically within a session to specific CDMA subscriber unit... |
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