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| Patent # | Description |
|---|---|
| US-9,502,802 |
Apparatus and method for using conductive adhesive fibers as a data
interface An apparatus and method for using conductive adhesive fibers as a data interface are disclosed. A particular embodiment includes: a first array of conductive... |
| US-9,502,800 |
Double-mated edge finger connector A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a... |
| US-9,502,568 |
Non-planar quantum well device having interfacial layer and method of
forming same Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V... |
| US-9,502,368 |
Picture frame stiffeners for microelectronic packages A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An... |
| US-9,502,359 |
Integrated circuit component shielding Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a... |
| US-9,502,336 |
Coreless substrate with passive device pads Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with... |
| US-9,502,281 |
AVD hardmask for damascene patterning A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a... |
| US-9,502,139 |
Fine grained online remapping to handle memory errors An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is... |
| US-9,502,118 |
NAND memory addressing Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory... |
| US-9,502,108 |
Programming memory cells using a program pulse Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse. |
| US-9,502,104 |
Multi-level cell (MLC) non-volatile memory data reading method and
apparatus Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one... |
| US-9,502,082 |
Power management in dual memory platforms Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch,... |
| US-9,501,864 |
Adaptive depth offset compression Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed... |
| US-9,501,860 |
Sparse rasterization An importance map indicates, for each of a plurality of pixels, whether the pixel is considered important enough to be rendered. A hierarchical tree for pixels... |
| US-9,501,830 |
Blob detection in noisy images Techniques related to blob detection in noisy images are discussed. Such techniques may include traversing a contour associated with a candidate blob contour... |
| US-9,501,826 |
Rectification techniques for heterogeneous camera arrays Rectification techniques for camera arrays in which the resolutions, fields of view, and/or pixel sizes of various cameras may differ from one another are... |
| US-9,501,716 |
Labeling component parts of objects and detecting component properties in
imaging data Techniques related to labeling component parts and detecting component properties in imaging data are discussed. Such techniques may include generating a... |
| US-9,501,669 |
Method and apparatus for location-based recovery of stolen mobile devices A method, apparatus, and system for locating mobile devices. The system includes a location-aware mobile device. The location-aware mobile device includes a... |
| US-9,501,668 |
Secure video ouput path Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected... |
| US-9,501,665 |
Method and apparatus for remotely provisioning software-based security
coprocessors A virtual security coprocessor is created in a first processing system. The virtual security coprocessor is then transferred to a second processing system, for... |
| US-9,501,637 |
Hardware shadow stack support for legacy guests Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call... |
| US-9,501,472 |
System and method for dual screen language translation Generally, this disclosure provides systems and methods to facilitate real-time language translation between two speakers. A system may include an audio... |
| US-9,501,421 |
Memory sharing and page deduplication using indirect lines Memory management includes maintaining a plurality of physical pages corresponding to a respective plurality of indirect lines, where each of the plurality of... |
| US-9,501,405 |
Flexible wear management for non-volatile memory Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems... |
| US-9,501,402 |
Techniques to perform power fail-safe caching without atomic metadata A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a... |
| US-9,501,376 |
Testing I/O timing defects for high pin count, non-contact interfaces Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line... |
| US-9,501,340 |
Mechanism for facilitating dynamic and efficient management of instruction
atomicity violations in software... A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment.... |
| US-9,501,299 |
Minimizing performance loss on workloads that exhibit frequent core
wake-up activity A processor may include a cause agnostic frequency dither filter (FD filter), which may cause reduction in the frequency transitions while maintaining the... |
| US-9,501,281 |
Method and apparatus for performing a shift and exclusive or operation in
a single instruction Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In... |
| US-9,501,276 |
Instructions and logic to vectorize conditional loops Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to... |
| US-9,501,182 |
Mechanism for interpreting touches to a pad cover over a sensor pad at a
computing device A mechanism is described for interpreting touches to a pad cover placed over a sensor external to a computing device. A method of embodiments of the invention... |
| US-9,501,178 |
Generating audible tooltips A processor-based system may include software which implements an audible tooltip. For example, in connection with a touch screen display, when an object is... |
| US-9,501,175 |
Techniques and apparatus for managing touch interface An apparatus may comprise a touch-sensitive user interface, a processor circuit; and a personalized touch event filter that includes a touch trainer module for... |
| US-9,501,135 |
Dynamic core selection for heterogeneous multi-core systems Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a... |
| US-9,501,132 |
Instruction and logic for store broadcast and power management A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit.... |
| US-9,501,129 |
Dynamically adjusting power of non-core processor circuitry including
buffer circuitry In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion... |
| US-9,501,125 |
Systems and methods for implementing reduced power states In some embodiments, provided is a way for devices to request S0ix (or the like) entry and exit. |
| US-9,501,112 |
Thermal energy storage, dissipation and EMI suppression for integrated
circuits using porous graphite sheets... Mobile platforms and methods may provide for an integrated circuit such as a system on chip (SoC), a first heat spreader thermally coupled to the integrated... |
| US-9,501,105 |
Keyboard for an electronic device Particular embodiments described herein provide for a keyboard that includes a plurality of keys; and a plurality of key actuators. At least a portion of the... |
| US-9,501,068 |
Integration of pressure sensors into integrated circuit fabrication and
packaging A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A... |
| US-9,500,827 |
Apparatus, method and system for spectrometry with a displaceable
waveguide structure Techniques and mechanisms for a monolithic photonic integrated circuit (PIC) to provide spectrometry functionality. In an embodiment, the PIC comprises a... |
| US-9,500,714 |
Power consumption monitoring device for a power source Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or... |
| US-9,500,617 |
Nanogap transducers with selective surface immobilization sites Embodiments of the invention provide transducers capable of functioning as electronic sensors and redox cycling sensors. Transducers comprise two electrodes... |
| US-9,499,995 |
Coverage extension level for coverage limited device Generally discussed herein are systems, apparatuses, and methods that can provide a coverage enhancement to a coverage limited device. According to an example a... |
| US-9,499,578 |
Massively parallel synthesis of biopolymeric arrays Methods for fabricating dense arrays of polymeric molecules in a highly multiplexed manner are provided using semiconductor-processing-derived lithographic... |
| US-D772,481 |
Applicator |
| US-D772,186 |
Wireless electronic video device |
| US-9,497,797 |
Radio communication devices and methods for operating radio communication
devices A radio communication device is described having a first transceiver configured to transmit and receive signals in accordance with a Cellular Wide Area radio... |
| US-9,497,785 |
Techniques for exchanging beamforming information for a dual connection to
user equipment Examples are disclosed for exchanging beamforming information for a first wireless link utilized as a first connection of a dual connection for user equipment... |
| US-9,497,762 |
Multicarrier techniques for wireless systems Multicarrier techniques for wireless communications system are described. An apparatus may comprise a carrier management module to define a primary carrier for... |
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