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Patent # Description
US-8,279,935 Method and apparatus for image quality control in video data
In one embodiment of the invention, a method for controlling video image quality may include receiving digital video data into a buffer that is coupled to a...
US-8,279,913 Configurable transceiver
A system is disclosed for operating a plurality of receiver paths and/or a plurality of transmitter paths in a single mode or multiple mode configuration.
US-8,279,886 Dataport and methods thereof
A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for...
US-8,279,813 Method and apparatus of subchannelization of wireless communication system
A method and apparatus to transmit pilot subcarriers over uplink channels. The pilot subcarriers includes symbols which hierarchically structured. The symbol...
US-8,279,790 Packet buffering based at least in part upon packet receipt time interval weighted moving average
An embodiment may include circuitry to be comprised in a node. The node may be communicatively coupled to a network and may include a host processor to execute...
US-8,279,689 Low power termination for memory modules
An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first...
US-8,279,355 Method and apparatus to support multi-channel reception
In accordance with various aspects of the disclosure, a method and apparatus for receiving multiple channels from a broadcast source and interfacing to multiple...
US-8,279,240 Video scaling techniques
A video scaler is disclosed. A polyphase filter can be used to generate interpolated pixels. The values of pixels adjacent an interpolated pixel are examined to...
US-8,279,213 Synchronized media processing
An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of...
US-8,278,752 Microelectronic package and method for a compression-based mid-level interconnect
A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first...
US-8,278,741 Sidewall photodetector
Sidewall photodetectors for integrated photonic devices and their method of manufacture. An embodiment includes a p-i-n film stack formed on a sidewall of a...
US-8,278,718 Stressed barrier plug slot contact structure for transistor performance enhancement
A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact...
US-8,278,692 Soft error reduction circuit and method
In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some...
US-8,278,687 Semiconductor heterostructures to reduce short channel effects
Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or...
US-8,278,641 Fabricating current-confining structures in phase change memory switch cells
In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment...
US-8,278,214 Through mold via polymer block package
Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first...
US-8,278,121 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode...
US-8,278,055 Methods and device for analyte characterization
The methods and apparatus, disclosed herein are of use for sequencing and/or identifying proteins, polypeptides and/or peptides. Proteins containing labeled...
US-8,276,269 Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making same
A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting...
US-8,276,262 Magnetically coupled thin-wafer handling system
Aspects of the present disclosure may include an apparatus for enclosing a thin wafer to prevent damage during an on-going manufacture of integrated circuit...
US-8,276,208 Security-level enforcement in virtual-machine fail-over
Methods, systems, and articles to receive, by a fail-over computing device, a request to instantiate a virtual-machine in response to a virtual-machine failure...
US-8,276,149 Thread livelock reduction unit
Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least...
US-8,276,142 Hardware support for thread scheduling on multi-core processors
A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The...
US-8,276,127 Devices, methods and computer program products for reverse execution of a simulation
Devices, methods, and software program products for reverse execution of a simulation and/or tracing a value are provided. A state of a preceding checkpoint may...
US-8,276,028 Using error information from nearby locations to recover uncorrectable data in non-volatile memory
In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an...
US-8,276,004 Systems and methods for energy efficient load balancing at server clusters
Methods and systems to balance the load among a set of processing units, such as servers, in a manner that allows the servers periods of low power consumption....
US-8,275,942 Performance prioritization in multi-threaded processors
According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware...
US-8,275,805 Method of decreasing a total computation time for a visual simulation loop in a virtual world application
A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation...
US-8,275,599 Embedded bus emulation
A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body....
US-8,275,560 Power measurement techniques of a system-on-chip (SOC)
A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full...
US-8,275,378 Handover for cellular radio communications
An improved handover process is described for a cellular wireless network. In one example, a method includes registering a mobile station to a first base...
US-8,275,057 Methods and systems to estimate channel frequency response in multi-carrier signals
Methods and systems to determine channel frequency responses corresponding to multi-carrier signals, such as OFDM signals, including to filter or mask noise...
US-8,275,028 Advanced television systems committee (ATSC) digital television (DTV) receiver
A computer system may comprise a receiver to perform equalization. The receiver comprises an equalizer. The equalizer may determine locations of a principal...
US-8,274,908 Quality of service packet processing without explicit control negotiations
Apparatuses, methods, systems, and computer program products to process QoS packets of wireless traffic without explicit control negotiations are disclosed. An...
US-8,274,501 Techniques to control self refresh display functionality
Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is...
US-8,274,339 Automatic frequency control architecture with digital temperature compensation
A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments...
US-8,274,308 Method and apparatus for dynamic memory termination
Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory...
US-8,274,228 Flow tube apparatus
A flow tube apparatus may include a flow tube having a first opening and a second opening, a corona electrode provided in the flow tube, a collecting electrode...
US-8,273,626 Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top...
US-8,273,242 Nanofabricated structures for electric field-assisted nucleic acid extraction
Embodiments of the invention provide devices and methods for extracting nucleic acid molecules from solution using electric fields. The structures and methods...
US-8,272,781 Dynamic power control of a memory device thermal sensor
Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In...
US-8,271,986 Visual and graphical data processing using a multi-threaded architecture
Active and/or proactive semaphore mechanisms and thread synchronization techniques can be applied to various visual and graphical processing techniques.
US-8,271,978 Virtualization event processing in a layered virtualization architecture
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an...
US-8,271,850 Fast low-density parity-check code encoder
Methods, apparatus, and systems are provided to encode a low-density parity-check codeword for transmission in a communications channel. In an embodiment, the...
US-8,271,748 Generating and/or receiving, at least one data access request
In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to...
US-8,271,732 System and method to reduce power consumption by partially disabling cache memory
In one embodiment, a cache memory includes a data array having N ways and M sets and at least one fill buffer coupled to the data array, where the data array is...
US-8,271,715 Modular scalable PCI-Express implementation
In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers...
US-8,271,694 Method and apparatus for using a single multi-function adapter with different operating systems
A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating...
US-8,271,605 System and method for managing distributed objects as a single representation
An architecture and method for managing at least two distinct machines (or objects) in which resources are shared as a single entity (or object) in an...
US-8,271,570 Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography
A unified integer/Galois-Field 2.sup.m multiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key...
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