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| Patent # | Description |
|---|---|
| US-9,369,774 |
System and method for controlling home network devices using multicast
enabled remote controls A system, method, and article of manufacture for controlling home network devices using a multicast enabled remote control. The system includes a plurality of... |
| US-9,369,735 |
Method and apparatus for adaptively reducing artifacts in block-coded
video Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes... |
| US-9,369,727 |
Storage of depth information in a digital image file Techniques are disclosed for encoding depth-enabled digital images in a file format, such as JPEG. In addition to compressed image data, calibration, disparity... |
| US-9,369,661 |
Real-time interactive personal video recorder interface Interacting with a television program includes beginning playback of the program for perception by a user, analyzing the program to detect a cue within the... |
| US-9,369,551 |
Apparatus, system and method of protocol adaptation layer (PAL)
communication to indicate transitioning a... Some demonstrative embodiments include apparatuses, systems and/or methods of transitioning a device to a default state. For example, an apparatus may include a... |
| US-9,369,522 |
Scalable network apparatus for content based switching or validation
acceleration A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded... |
| US-9,369,441 |
End-to-end secure communication system The present disclosure is directed to an end-to-end secure communication system wherein, in addition to encrypting transmissions between clients, ... |
| US-9,369,277 |
Encryption code generation using spin-torque NANO-oscillators Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first... |
| US-9,369,235 |
Maximizing data rate by adjusting codes and code rates The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate... |
| US-9,369,225 |
Distribution of an electronic reference clock signal that includes delay
and validity information An integrated circuit has a clock subsystem, and a circuit. The clock subsystem is configured to provide a reference clock signal to a first module and a second... |
| US-9,369,217 |
Cellular up-link harmonic spurs mitigation in Wi-Fi and bluetooth
receivers An interfering signal from a co-running modem is filtered using a notch filter to cancel high frequency harmonic interference to a received radio frequency (RF)... |
| US-9,369,188 |
Link prediction based re-beamforming triggering algorithm for 60 ghz
communication links A system and method are provided to trigger re-beamforming based on an algorithm that assesses various link characteristics. The algorithm is based on the... |
| US-9,369,136 |
Digital phase controlled delay circuit An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from... |
| US-9,368,956 |
Electrostatic discharge clamp compatible with a fast ramping supply Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node... |
| US-9,368,861 |
Omni directional broadband coplanar antenna element The present invention provides an omni-directional antenna element configuration having a compensated radiation pattern. Broadband antenna elements are... |
| US-9,368,583 |
Field effect transistor with narrow bandgap source and drain regions and
method of fabrication A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer... |
| US-9,368,461 |
Contact pads for integrated circuit packages Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a... |
| US-9,368,455 |
Electromagnetic interference shield for semiconductor chip packages An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a package has a semiconductor die. a redistribution... |
| US-9,368,437 |
High density package interconnects Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die... |
| US-9,368,429 |
Interposer for hermetic sealing of sensor chips and for their integration
with integrated circuit chips Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an... |
| US-9,368,401 |
Embedded structures for package-on-package architecture Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer... |
| US-9,368,290 |
Charge storage device, method of making same, method of making an
electrically conductive structure for same,... In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator... |
| US-9,368,208 |
Non-volatile latch using magneto-electric and ferro-electric tunnel
junctions A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power... |
| US-9,368,205 |
Set and reset operation in phase change memory and associated techniques
and configurations Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an... |
| US-9,367,948 |
Flexible filter logic for multi-mode filtering of graphical texture data Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of... |
| US-9,367,916 |
Method and system of run-time self-calibrating lens shading correction A system, article, and method of run-time self-calibrating lens shading correction. |
| US-9,367,898 |
Orientation of display rendering on a display based on position of user Apparatus, computer-readable storage medium, and method associated with orienting a display image are described. In embodiments, a computing device may include... |
| US-9,367,731 |
Depth gradient based tracking Systems and methods may provide for determining depth gradient information based on a depth map of a scene, and determining a threshold parameter. Additionally,... |
| US-9,367,688 |
Providing geographic protection to a system In one embodiment, a method includes determining a location of a system responsive to location information received from at least one of a location sensor and a... |
| US-9,367,500 |
Apparatus for multiple bus master engines to share the same request
channel to a pipelined backbone In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined... |
| US-9,367,477 |
Instruction and logic for support of code modification in translation
lookaside buffers A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory... |
| US-9,367,464 |
Cache circuit having a tag array with smaller latency than a data array A method is described that includes alternating cache requests sent to a tag array between data requests and dataless requests. |
| US-9,367,406 |
Manageability redundancy for micro server and clustered system-on-a-chip
deployments Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable... |
| US-9,367,329 |
Initialization of multi-core processing system This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using... |
| US-9,367,328 |
Out-of-band host OS boot sequence verification Embodiments of techniques and systems for out-of-band verification of host OS components are described. In embodiments, a out-of-band host OS boot sequence... |
| US-9,367,327 |
Method to ensure platform silicon configuration integrity Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the... |
| US-9,367,325 |
Common architecture state presentation for processor having processing
cores of different types A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes... |
| US-9,367,317 |
Loop streaming detector for standard and complex instruction types A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is... |
| US-9,367,314 |
Converting conditional short forward branches to computationally
equivalent predicated instructions A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The... |
| US-9,367,280 |
Dual screen visibility with virtual transparency Generally, this disclosure provides devices, systems and methods to provide dual screen visibility with virtual transparency. A device may include a dual-sided... |
| US-9,367,174 |
Wireless peripheral data transmission for touchscreen displays Embodiments of the disclosure describe data transmission via a touchscreen display of a mobile computing device. The mobile computing device includes a... |
| US-9,367,116 |
Apparatus to reduce idle link power in a platform A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root... |
| US-9,367,114 |
Controlling operating voltage of a processor In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to... |
| US-9,367,112 |
Optimizing power usage by factoring processor architectural events to PMU A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural... |
| US-9,367,101 |
Passive noise cancellation for computer cooling systems Methods and systems may provide for a computing system including an electrical component, a heat exchanger coupled to the electrical component, and a fan having... |
| US-9,367,080 |
Apparatus, system, and method for providing clock signal on demand Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in... |
| US-9,367,078 |
Modification of indicators corresponding to alerts Various methods and systems for modifying an indicator corresponding to an alert are described herein. One example method includes detecting an alert with a... |
| US-9,366,482 |
Adjustable heat pipe thermal unit Assemblies and methods are described. One assembly includes a first plate and a second plate. The assembly also includes an adjustable heat pipe positioned... |
| US-D759,029 |
Computer on a stick |
| US-D759,027 |
PC on a stick |
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