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| Patent # | Description |
|---|---|
| US-9,544,419 |
Methods and systems for configuring a mobile device based on an
orientation-based usage context Disclosed is an apparatus and method for automatically configuring a mobile device. A mobile device can include a touch sensitive display, a processor, and a... |
| US-9,544,418 |
Dual communication circuit device selecting communication circuit based on
communication activity history A communication device may be provided. The communication device may include a first communication circuit configured to perform a first communication activity;... |
| US-9,544,417 |
System and method for sending local information from a wireless browser to
a web server A system and method for using a wireless browser to send local information from a wireless handset to a Web server. A service request received from a handset... |
| US-9,544,347 |
Distributing intelligence across networks Methods and apparatus relating to distribution of intelligence across a network are described. In one embodiment, one or more content processors may be provided... |
| US-9,544,319 |
Anomaly detection on web client Embodiments for anomaly detection on a web client are generally described herein. A processor on the web client is monitored, where a web browser is installed... |
| US-9,544,272 |
Detecting image spam Methods and systems for operation upon one or more data processors for detecting image spam by detecting an image and analyzing the content of the image to... |
| US-9,544,141 |
Secure key storage using physically unclonable functions Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include... |
| US-9,544,139 |
Method and apparatus for a non-deterministic random bit generator (NRBG) A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition... |
| US-9,544,133 |
On-the-fly key generation for encryption and decryption Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one... |
| US-9,544,121 |
Methods and devices for determining effective mutual information A method includes receiving at a receiver circuit a composite signal including non-interfered data resource elements and interfered data resource elements from... |
| US-9,544,100 |
Techniques to stop transmission of data based on reception of an
acknowledgment within a specified time Examples are disclosed for simultaneous transmitting and receiving packets in a wireless local access network (WLAN). In some examples, a source node in the... |
| US-9,544,099 |
User equipment, evolved node B, and method for multicast device-to-device
communications Apparatuses and methods for supporting multicast device-to-device communications are described herein. A user equipment (UE) may transmit a request to a serving... |
| US-9,544,089 |
Techniques to perform forward error correction for an electrical backplane A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward... |
| US-9,544,072 |
Virtualization of natural radio environments to test a radio device Natural radio environments are virtualized to test radio devices. In one example, this is done by extracting signals and messages recorded in the field and... |
| US-9,544,002 |
Concurrent transmit and receive The disclosure is directed to a circuit arrangement and method that provide efficient concurrent transmit and receive, transmit only and receive only of... |
| US-9,543,956 |
Systems and methods for configuring an SOPC without a need to use an
external memory Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input... |
| US-9,543,515 |
Electrode materials and interface layers to minimize chalcogenide
interface resistance A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An... |
| US-9,543,507 |
Selector for low voltage embedded memory Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is... |
| US-9,543,272 |
Method for interconnecting stacked semiconductor devices A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The... |
| US-9,543,261 |
Designs and methods for conductive bumps Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor... |
| US-9,543,244 |
Hybrid package transmission line circuits "Hybrid" transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are... |
| US-9,543,224 |
Hybrid exposure for semiconductor devices Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include... |
| US-9,543,197 |
Package with dielectric or anisotropic conductive (ACF) buildup layer Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to... |
| US-9,543,024 |
Nonvolatile memory erasure techniques Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before... |
| US-9,543,019 |
Error corrected pre-read for upper page write in a multi-level cell memory Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of... |
| US-9,543,005 |
Multistage memory cell read A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce... |
| US-9,543,004 |
Provision of holding current in non-volatile random access memory Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In... |
| US-9,542,929 |
Systems and methods for providing non-lexical cues in synthesized speech Systems and methods for providing non-lexical cues in synthesized speech are described herein. Original text is analyzed to determine characteristics of the... |
| US-9,542,776 |
Generating random sampling distributions using stochastic rasterization Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling... |
| US-9,542,774 |
Determining a node paththrough a node graph Determining a node path through a node graph includes modifying the node graph in accordance with a predetermined platform performance, performing a path... |
| US-9,542,718 |
Head mounted display update buffer Techniques related to providing updates in a head mounted display (HMD) device are described herein. A HMD may be configured to display a view of an... |
| US-9,542,561 |
Instructions processors, methods, and systems to process secure hash
algorithms A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a.sub.i,... |
| US-9,542,522 |
Interconnect routing configurations and associated techniques Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus... |
| US-9,542,356 |
Determining, at least in part, one or more respective amounts of buffer
memory An embodiment may include determining at least one respective amount of buffer memory to be used to store at least one respective portion of network traffic.... |
| US-9,542,347 |
Host interface crossbar for sensor hub A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager... |
| US-9,542,336 |
Isochronous agent data pinning in a multi-level memory system A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by... |
| US-9,542,325 |
Adjustable over-restrictive cache locking limit for improved overall
performance Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from... |
| US-9,542,211 |
Co-designed dynamic language accelerator for a processor In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output... |
| US-9,542,196 |
Communication terminal and method for providing configuration data for a
modem with system boot firmware A communication terminal is described comprising a modem; a first memory configured to store configuration data for the modem; a second memory configured to... |
| US-9,542,193 |
Memory address collision detection of ordered parallel threads with bloom
filters A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store... |
| US-9,542,191 |
Hardware profiling mechanism to enable page level automatic binary
translation A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime... |
| US-9,542,186 |
Instruction set for supporting wide scalar pattern matches A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit... |
| US-9,542,154 |
Fused multiply add operations using bit masks Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is... |
| US-9,542,150 |
Controlling audio players using environmental audio analysis A method, system, and computer program product containing instructions for analyzing audio input to a receiver coupled to an audio player to identify an audio... |
| US-9,542,123 |
Disabling a command associated with a memory device In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation... |
| US-9,542,114 |
Methods and apparatus to protect memory regions during low-power states A disclosed example involves managing power states, signing a suspend-to-RAM (STR) data structure by: generating a header key, a scatter/gather table key and a... |
| US-9,541,993 |
Mobile device operation using grip intensity Mobile device operation using grip intensity. An embodiment of a mobile device includes a touch sensor to detect contact or proximity by a user of the mobile... |
| US-9,541,991 |
Method and apparatus for managing computing system power An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage... |
| US-9,541,987 |
Generic host-based controller latency method and appartus Methods and apparatus relating to generic host-based controller latency are described. In one embodiment, latency information, corresponding to one or more... |
| US-9,541,983 |
Controlling reduced power states using platform latency tolerance In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event... |
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