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Patent # Description
US-9,335,813 Method and system for run-time reallocation of leakage current and dynamic power supply current
A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention,...
US-9,335,808 Indicating critical battery status in mobile devices
An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The...
US-9,335,804 Distributing power to heterogeneous compute elements of a processor
In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute...
US-9,335,803 Calculating a dynamically changeable maximum operating voltage value for a processor based on a different...
In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of...
US-9,335,373 Memory channel having deskew separate from redrive
A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from...
US-9,332,643 Interconnect architecture with stacked flex cable
Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the...
US-9,332,564 Method, apparatus and system to manage distributed channel access with time reservation
A method, apparatus and system to manage distributed channel access with time reservation are generally presented. In this regard, a reservation agent is...
US-9,332,551 Opportunistic resource sharing between devices
Techniques for opportunistic resource sharing between mobile devices are described. A method comprises identifying a set of homogeneous device resources...
US-9,332,469 Frequency offset measurement enhancements for long term evolution (LTE)
Embodiments for providing frequency offset measurement enhancements are generally described herein. In some embodiments, user equipment is informed of a...
US-9,332,456 Discontinuous reception (DRX) enhancements in LTE systems
Embodiments of a system and method for providing DRX enhancements in LTE systems are generally described herein. In some embodiments, a system control module is...
US-9,332,452 Radio communication devices and methods for controlling a radio communication device
A radio communication device may be provided. The radio communication device may include: a measurement circuit configured to measure a first reception quality...
US-9,332,451 Method and apparatus of requesting a beacon report
A beacon signal may be provided with data extensions. The data extensions permit additional information to be provided by the beacon signal, thereby reducing...
US-9,332,417 Apparatuses and methods for coordinating operations of multiple wireless communications modules with multiple...
A wireless communications device is provided with a plurality of card slots, a first wireless communications module, and a second wireless communications...
US-9,332,381 Location-based application recommendation
Described herein are techniques related to location-aware application recommendations in wireless devices. For example, an application recommendation alert may...
US-9,332,264 Configurable performance motion estimation for video encoding
A motion estimation engine may be implemented to include a skip checking module, an integer search module, a macroblock partitioning module, a fractional search...
US-9,331,935 Network device selection
An embodiment may include circuitry that may be capable of selecting, from network devices, at least one network device to which at least one packet is to be...
US-9,331,855 Apparatus, system, and method for providing attribute identity control associated with a processor
Described herein are an apparatus, system, and method for attribute identity control in a processor. The apparatus comprises a logic unit including a...
US-9,331,814 Hybrid automatic repeat-request combination for wireless transmissions
In one embodiment, a method for data communication may include receiving a first set of soft bit values in a Hybrid Automatic Repeat-Request (HARQ) buffer using...
US-9,331,795 Transmission arrangement and method for analyzing an amplified transmission signal
A transmission arrangement is disclosed having an amplifier which is set up to amplify a transmission signal and to provide it as an amplified transmission...
US-9,331,759 HARQ timing design for a TDD system
Disclosed are methods and apparatuses related to receiving one or more indications of time division duplex (TDD) uplink/downlink (UL/DL) configurations for two...
US-9,331,722 Feedback calibration of digital to time converter
This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include...
US-9,331,674 Multi-phase signal generator and multi-phase signal generating method thereof
A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first...
US-9,331,017 Chip package incorporating interfacial adhesion through conductor sputtering
This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an...
US-9,330,999 Multi-component integrated heat spreader for multi-chip packages
A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the...
US-9,330,993 Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
US-9,330,963 Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
US-9,330,827 Method of manufacturing inductors for integrated circuit packages
A process of making inductors for integrated circuit packages may involve forming an inductor upon a magnetic film on a package substrate. Conductors coupled...
US-9,330,784 Dynamic window to improve NAND endurance
Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated...
US-9,330,747 Non-volatile latch using spin-transfer torque memory device
Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first ...
US-9,330,734 Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The...
US-9,330,718 Techniques for adding interactive features to videos
Techniques are disclosed for adding interactive features to videos to enable users to create new media using a dynamic blend of motion and still imagery. The...
US-9,330,483 Avatar facial expression techniques
A method and apparatus for capturing and representing 3D wireframe, color and shading of facial expressions are provided, wherein the method includes the...
US-9,330,478 Augmented reality creation using a real scene
The creation of augmented reality is described using a real scene. In one example, a process includes observing a real scene through a camera of a device,...
US-9,330,470 Method and system for modeling subjects from a depth map
A method for modeling and tracking a subject using image depth data includes locating the subject's trunk in the image depth data and creating a...
US-9,330,433 Data distribution fabric in scalable GPUs
In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data...
US-9,330,394 Content management with hierarchical content rules
Computing apparatus, computer-readable storage medium, and method associated with application of content rules to content. The computing apparatus may have a...
US-9,330,379 Providing notifications of messages for consumption
Embodiments of apparatus, packages, computer-implemented methods, systems, devices, and computer-readable media (transitory and non-transitory) are described...
US-9,330,363 Method and article of manufacture for ensuring fair access to information using propagation delays to determine...
Locks placed on corresponding objects held in a plurality of databases located at different nodes in a network during replication are released in accordance...
US-9,330,322 Controlled access to functionality of a wireless device
Various embodiments of the invention may be used to verify that a person being authorized by biometric techniques to use a device is a living person and not...
US-9,330,112 Grouping and compressing similar photos
Systems and methods may provide for assigning a subset of a plurality of photos to a group and selecting a reference photo from the group. Additionally, the...
US-9,330,039 Crosstalk aware encoding for a data bus
Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a...
US-9,330,028 Instruction and logic for a binary translation mechanism for control-flow security
A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the...
US-9,330,027 Register access white listing
A system employs a white list of authorized transactions to control access to system registers. In an embodiment, the white list is loaded into filter registers...
US-9,330,022 Power logic for memory address conversion
In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated...
US-9,330,021 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,330,020 System, apparatus, and method for transparent page level instruction translation
Detailed herein are systems, apparatuses, and methods for transparent page level instruction translation. Exemplary embodiments include an instruction...
US-9,329,974 Technologies for determining binary loop trip count using dynamic binary instrumentation
Technologies for binary loop trip count computation include a computing device that dynamically instruments binary code, executes the instrumented code, and...
US-9,329,936 Redundant execution for reliability in a super FMA ALU
A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the...
US-9,329,918 Resilient register file circuit for dynamic variation tolerance and method of operating the same
The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage...
US-9,329,900 Hetergeneous processor apparatus and method
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more...
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