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Patent # Description
US-1,038,7305 Techniques for compression memory coloring
Techniques and computing devices for compression memory coloring are described. In one embodiment, for example, an apparatus may include at least one memory, at...
US-1,038,7304 Virtual transfer of data between memory and storage domains
Devices, systems, and methods for transferring data between the memory domain and the storage domain are described. Transferring data between domains can...
US-1,038,7296 Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions
Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are...
US-1,038,7259 Instant restart in non volatile system memory computing systems with embedded programmable data checking
An apparatus is described. The apparatus includes a memory controller having a programmable component. The programmable component is to implement a data...
US-1,038,7216 Task mapping for heterogeneous platforms
An exemplary system according to various examples receives a function call including a plurality of operands, each operand in the plurality of operands...
US-1,038,7182 Direct memory access (DMA) based synchronized access to remote device
Methods, systems, or apparatus may be directed to hosting, by a virtual machine manager of a local machine, a virtual machine having a device driver. A virtual...
US-1,038,7160 Shared local memory tiling mechanism
An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing...
US-1,038,7159 Apparatus and method for architectural performance monitoring in binary translation systems
Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an...
US-1,038,7158 Systems, apparatuses, and methods for data speculation execution
Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a...
US-1,038,7156 Systems, apparatuses, and methods for data speculation execution
Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a...
US-1,038,7151 Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory...
Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address...
US-1,038,7149 Apparatus and method to reverse and permute bits in a mask register
An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an...
US-1,038,7148 Apparatus and method to reverse and permute bits in a mask register
An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an...
US-1,038,7072 Systems and method for dynamic address based mirroring
A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store...
US-1,038,7037 Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read...
Techniques for enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies are disclosed. A hardware processor includes...
US-1,038,6941 Gyratory sensing system to enhance wearable device user experience via HMI extension
Methods and systems may provide for a gyratory sensing system (GSS) for extending the human machine interface (HMI) of an electronic device, particularly small...
US-1,038,6926 Haptic mapping
Systems, apparatuses, and methods may include recording forces from manipulation of a three-dimensional object by a haptic user interface and generating a...
US-1,038,6915 Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate...
US-1,038,6908 Negotiating a transmit wake time
Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive...
US-1,038,6900 Thread aware power management
In an embodiment, a power management controller is to receive thread information from a scheduler, where the thread information includes thread priority...
US-1,038,6842 Unmanned aerial vehicle light show
Herein is disclosed an unmanned aerial vehicle segment-imagery system comprising at least a first unmanned aerial vehicle and a second unmanned aerial vehicle,...
US-1,038,6833 Methods and apparatus for reducing energy consumed by drones during flight
Methods and apparatus for reducing energy consumed by drones during flight are disclosed. A drone includes a housing, a motor, and a route manager to generate a...
US-1,038,6722 Ebeam staggered beam aperture array
Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture...
US-1,038,6568 Combined rear cover and enhanced diffused reflector for display stack
Disclosed herein is a combined enhanced diffused reflector and back cover for a display stack. The back cover may be assembled proximate to a light guide panel...
US-1,038,6204 Integrated sensor and homologous calibration structure for resonant devices
An apparatus is provided which comprises: a substrate; a sensor including a sensing element, wherein the sensor is integrated within the substrate; and a...
US-1,038,4431 Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to...
A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot...
US-D857,007 Audio-visual display device
US-1,038,3080 Device and method to improve horizontal and vertical positioning accuracy
User equipment (UE), an enhanced NodeB (eNB) and method of improving positioning accuracy and enabling vertical domain positioning of the UE are generally...
US-1,038,3057 Multicast wakeup in wireless networks
The disclosure describes systems and methods for updating multicast wakeup schedules in devices in a mesh network such as a neighborhood area network (NAN)...
US-1,038,2344 Generating and/or receiving at least one packet to facilitate, at least in part, network path establishment
An embodiment may include circuitry to be included, at least in part, in at least one node in a network. The circuitry may generate, at least in part, and/or...
US-1,038,2181 Method and apparatus for supporting AMD re-segmentation
A method and apparatus for acknowledge mode data (AMD) re-segmentation are disclosed. An AMD protocol data unit (PDU) is generated from at least one RLC SDU....
US-1,038,2172 Hybrid orthogonal frequency division multiple access system and method
A hybrid orthogonal frequency division multiple access (OFDMA) system including a transmitter and a receiver is disclosed. The transmitter includes a first...
US-1,038,2144 Systems, methods, and devices for interference mitigation in wireless networks
Example systems, methods, and devices for mitigating interference in wireless networks are discussed. One example method includes the operations of passing...
US-1,038,2111 Beam interpolation in massive MIMO systems
Embodiments described herein include devices, methods, and instructions for managing beam interpolation in massive multiple-input multiple-output (MIMO)...
US-1,038,2107 Multi-user multiple input multiple output communication systems and methods
Embodiments provide methods for wireless Multi-User Multiple Input Multiple Output communications comprising creating a Demodulation reference signal (DM-RS);...
US-1,038,2019 Time borrowing flip-flop with clock gating scan multiplexer
An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain...
US-1,038,1986 Ultra compact multi-band transmitted with robust AM-PM distortion self-suppression techniques
A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the...
US-1,038,1678 Compressed Li-metal battery
A new battery cell structure uses a reduced stack pressure force to be used and applied over a much smaller area of the cells by using the sides of the cell...
US-1,038,1556 Spin transfer torque memory (STTM), methods of forming the same using a non-conformal insulator, and devices...
Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting...
US-1,038,1350 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-1,038,1310 Embedded multi-die interconnect bridge
The present disclosure relates to devices and techniques for an interconnect bridge to communicatively couple two or more dies. In an example, the interconnect...
US-1,038,1291 Lithographacally defined vias for organic package substrate scaling
Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric...
US-1,038,1288 Packaged semiconductor die and CTE-engineering die pair
Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For...
US-1,038,1086 Multiple blocks per string in 3D NAND memory
Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory...
US-1,038,1055 Flexible DLL (delay locked loop) calibration
A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can...
US-1,038,0896 Characterizing proximity risks within a radio mesh
Methods and apparatus relating to characterizing proximity risks within a radio mesh are described. In an embodiment, collection logic receives risk data from...
US-1,038,0789 Method and apparatus for efficient depth prepass
An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising:...
US-1,038,0713 Handling pipeline submissions across many compute units
One embodiment provides for a general-purpose graphics processing unit comprising multiple processing elements having a single instruction, multiple thread...
US-1,038,0496 Quantum computing assemblies
Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include...
US-1,038,0414 Method and system of facial expression recognition using linear relationships within landmark subsets
A system, article, and method to provide facial expression recognition using linear relationships within landmark subsets.
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