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Patent # Description
US-1,009,1122 Traffic management
One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to...
US-1,009,1074 Hardware acceleration architecture for signature matching applications for deep packet inspection
A signature matching hardware accelerator system comprising one or more hardware accelerator circuits, wherein each of the hardware accelerator circuit utilizes...
US-1,009,1063 Technologies for directed power and performance management
Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node....
US-1,009,1000 Techniques for distributing secret shares
Various embodiments are generally directed to an apparatus, method and other techniques generating one or more polynomial elements for a polynomial function...
US-1,009,0977 Techniques to manage dwell times for pilot rotation
Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of...
US-1,009,0964 Apparatus, computer readable medium, and method for an interleaver for higher quadrature amplitude modulation...
A high-efficiency wireless local-area network (HEW) device including physical layer and medium access control layer circuitry is disclosed. The physical layer...
US-1,009,0892 Apparatus and a method for data detecting using a low bit analog-to-digital converter
An apparatus and a method for detecting data transmitted over a wireless channel are disclosed. For example, for each receive antenna of a plurality of receive...
US-1,009,0854 Digital-to-analog converter and method for correcting gain mismatch between a first segment and a second...
A method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter is provided. The first segment generates a...
US-1,009,0840 Integrated circuits with programmable non-volatile resistive switch elements
Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive...
US-1,009,0808 Feed-forward envelope tracking
An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC)...
US-1,009,0713 Multiple coils for wireless power
A wireless power transfer device and method including a first coil of wire having a first winding to receive electrical current and emit a first electromagnetic...
US-1,009,0504 Non-uniform battery cell
An apparatus is provided that includes a two or more cell elements stacked internally to create a single cell with a non-uniform height. A first bus bar may...
US-1,009,0461 Oxide-based three-terminal resistive switching logic devices
Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are...
US-1,009,0405 Semiconductor device having group III-V material active region and graded gate dielectric
Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an...
US-1,009,0383 Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced...
US-1,009,0313 NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch....
US-1,009,0304 Isolation well doping with solid-state diffusion sources for FinFET architectures
An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that...
US-1,009,0277 3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package...
US-1,009,0261 Microelectronic package debug access ports and methods of fabricating the same
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
US-1,009,0259 Non-rectangular electronic device components
Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a...
US-1,009,0239 Metal-insulator-metal on-die capacitor with partial vias
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die....
US-1,009,0034 Magnetoelectric memory cells with domain-wall-mediated switching
A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain...
US-1,008,9964 Graphics processor logic for encoding increasing or decreasing values
Embodiments provide for a graphics processing apparatus comprising a graphics processing unit including bounding volume logic to encode a first bounding volume...
US-1,008,9962 Display interface partitioning
Various embodiments are generally directed to techniques to partition a display interface such that pixel data associated with display data having indications...
US-1,008,9779 Apparatus and method for conservative rasterization of polygons
An apparatus and method are described for conservative rasterization. For example, one embodiment of a graphics processing apparatus comprises: an edge tagging...
US-1,008,9750 Method and system of automatic object dimension measurement by using image processing
A system, article, and method of automatic object dimension measurement by using image processing.
US-1,008,9696 Budget-aware event information collection during program execution
Embodiments of techniques and systems for slowdown-budget-aware event information collection are described. In various embodiments, a system may be configured...
US-1,008,9500 Secure modular exponentiation processors, methods, systems, and instructions
A processor of an aspect includes a decode unit to decode a modular exponentiation with obfuscated input information instruction. The modular exponentiation...
US-1,008,9447 Instructions and logic to fork processes of secure enclaves and establish child enclaves in a secure enclave...
Instructions and logic fork processes and establish child enclaves in a secure enclave page cache (EPC). Instructions specify addresses for secure storage...
US-1,008,9270 Interchangeable power and signal contacts for IO connectors
Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a...
US-1,008,9264 Callback interrupt handling for multi-threaded applications in computing environments
A mechanism is described for facilitating callback interrupt handling for multi-threaded applications in computing environments. A method of embodiments, as...
US-1,008,9263 Synchronization of interrupt processing to reduce power consumption
A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first...
US-1,008,9247 System and method for coupling a host device to secure and non-secure devices
One embodiment provides an apparatus. The apparatus includes an input output memory management unit (I/O MMU), a non-secure operating system (OS) driver, a...
US-1,008,9244 Hardware for miss handling from a translation protection data structure
A processor includes a memory to store original code and a fingerprint data structure, which stores, in a way thereof, an entry including a physical address for...
US-1,008,9230 Resource-specific flushes and invalidations of cache and memory fabric structures
Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first...
US-1,008,9229 Cache allocation with code and data prioritization
Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to...
US-1,008,9207 Identification of software phases using machine learning
A computing device executes an application having a number of phases. The computing device collects performance data indicative of a number of performance...
US-1,008,9197 Leverage offload programming model for local checkpoints
Methods, apparatus, and systems for leveraging an offload programming model for local checkpoints. Compute entities in a computing environment are implemented...
US-1,008,9115 Apparatus to optimize GPU thread shared local memory access
One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single...
US-1,008,9113 Apparatus and method for low-latency invocation of accelerators
An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a...
US-1,008,9110 Systems, apparatuses, and methods for cumulative product
Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a...
US-1,008,9076 Floating point scaling processors, methods, systems, and instructions
A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or...
US-1,008,9075 Method and apparatus of instruction that merges and sorts smaller sorted vectors into larger sorted vector
A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum...
US-1,008,8880 Thermal monitoring of memory resources
Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may...
US-1,008,8864 Wireless gimbal connection for electronic devices
A wireless gimbal connection of use with electronics devices such as computer notebooks relatively pivotable portions such as a lid and base. The gimbal...
US-1,008,8518 Apparatus and method for classifying and locating electrical faults in circuitry
A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first...
US-1,008,8514 Orientation indicator with pin signal alteration
Techniques described herein include a method, system, and apparatus for detecting an orientation configuration. For example, an apparatus having an all-in-one...
US-1,008,8511 Estimation of complex antenna impedance using scalar measurements
Described herein are architectures, platforms and methods for deriving a complex antenna impedance based on scalar measurements. Three significantly different...
US-1,008,6479 High temperature solder paste
Embodiments herein may relate to a solder paste. The solder paste may include a solder powder and a flux. In embodiments, the flux may be a non-rosin based...
US-D829,707 Computer laptop assembly
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