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Method for performing mobile communications and mobile radio communication
A method for performing mobile communications from a first mobile terminal may include identifying one or more further mobile terminals engaged in...
HS-DSCH inter-node B cell change
A radio resource control (RRC) message is received by a radio resource control (RRC) device of a user equipment (UE). The RRC message notifies the FDD UE of a...
Loudspeaker cone excursion estimation using reference signal
The excursion of a loudspeaker cone is estimated using a reference signal in one example, a primary signal, produced by a cone of a loudspeaker, is received and...
Technologies for projecting a noncontinuous image
Technologies for projecting a noncontinuous image onto at least a portion of a projection region using a projector of a projection device. The projection device...
Multi-protocol I/O interconnect including a switching fabric
Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A...
Technologies for network packet cache management
Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network...
General input/output architecture, protocol and related methods to
implement flow control
A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a...
Hybrid I-Q polar transmitter with quadrature local oscillator (LO) phase
A hybrid polar I-Q transmitter comprises an I-Q quantization circuit configured to receive an in-phase signal and a quadrature signal forming a first I-Q data...
Adaptive serdes receiver
One embodiment provides an apparatus. The apparatus includes a feedforward equalizer (FFE), an FFE data slicer and an FFE least mean square (LMS) module. The...
Power saving mode optimizations and related procedures
Embodiments of an eNodeB and method for Machine Type Communication in a Wireless Network are generally described herein. In some embodiments, a method performed...
User equipment and method for assisted three dimensional beamforming
An embodiment for a method for user equipment assisted three-dimensional beamforming is disclosed. The method may include the user equipment receiving a...
Instruction and logic for accelerated compressed data decoding
A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value...
Electronic device having plurality of voltage rails
An electronic device may include a plurality of voltage rails to provide voltages to components of a load, a plurality of voltage regulators, and a buck...
Methods and systems for optimizing location-based wireless charging
Methods and systems for optimizing wireless charging are provided. The method may include identifying, by a charging controller, charging apparatus location...
Lightweight cavity filter structure
Embodiments provide a novel fabrication method and structure for reducing structural weight in radio frequency cavity filters and novel filter structure. The...
Shielding layer of battery cell structure
A battery cell structure may include a battery cell, a first pouch layer to substantially surround the battery cell, a second pouch layer to substantially...
Nanowire structures having non-discrete source and drain regions
Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked...
Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors...
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to...
Shaped and oriented solder joints
The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic...
An apparatus including a planar semiconductor substrate including a plurality of devices and a first pattern of electrical contacts formed on the first surface...
Crosstalk polarity reversal and cancellation through substrate material
Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane....
Methods of forming stacked microelectronic dice embedded in a
Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one...
Apparatus and method to monitor die edge defects
Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a...
Integrated circuit defect detection and repair
In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in...
Method, apparatus and system for responding to a row hammer event
Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the...
Limiting peak audio power in mobile devices
Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a...
Efficient free-space finger recognition
Systems and techniques for efficient free-space finger recognition are herein described. A surface in a depth image may be identified. One or more blobs in the...
Techniques to request stored data from memory
Techniques are described to generate an index for a texture. The index can be used to retrieve a portion of one or more textures from a cache. The index can be...
Techniques for clearing a shared surface
Various embodiments are generally directed to an apparatus, method and other techniques to determine that a shared surface is shared between a first application...
Using a generic classifier to train a personalized classifier for wearable
Systems and methods may provide for using one or more generic classifiers to generate self-training data based on a first plurality of events associated with a...
Method, apparatus and computer readable recording medium for detecting a
location of a face feature point using...
The present disclosure relates to detecting the location of a face feature point using an Adaboost learning algorithm. According to some embodiments, a method...
Security co-processor boot performance
Technologies for improving platform initialization on a computing device include beginning initialization of a platform of the computing device using a basic...
Methods and apparatus to manage password security
Methods, apparatus, systems and articles of manufacture are disclosed to manage password security. An example apparatus includes an alarm action engine to...
Automatic metatagging in images
Various systems and methods for implementing automatic image metatagging are described herein. A system for metatagging media content comprises a camera system;...
Method, apparatus, system for representing, specifying and using deadlines
In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated...
System and methods exchanging data between processors through concurrent
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
Cache allocation with code and data prioritization
Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to...
Initiation of cache flushes and invalidations on graphics processors
Methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and using a kernel on the graphics processor to issue a...
Instruction and logic for flush-on-fail operation
A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to...
Performing concurrent rehashing of a hash table for multithreaded
In one embodiment, the present invention includes a method for allocating a second number of buckets for a hash table shared concurrently by a plurality of...
Method and apparatus for supporting programmable software context state
execution during hardware context...
A method and apparatus for supporting programmable software context state execution during hardware context restore flow is described. In one example, a context...
Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and...
Technologies for pre-memory phase initialization of a computing device
Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a...
Techniques for cooperative execution between asymmetric processor cores
Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of...
Coalescing adjacent gather/scatter operations
According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first...
Instruction and logic to provide pushing buffer copy and store
Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second...
Graphics processor sub-domain voltage regulation
Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be...
Systems, apparatuses, and methods for synchronizing port entry into a low
Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state...
Processor hiding its power-up latency with activation of a root port and
quickly sending a downstream cycle
Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing...