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| Patent # | Description |
|---|---|
| US-9,614,119 |
Avalanche photodiode with low breakdown voltage An Si/Ge SACM avalanche photo-diodes (APD) having low breakdown voltage characteristics includes an absorption region and a multiplication region having various... |
| US-9,614,093 |
Strain compensation in transistors Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The... |
| US-9,614,083 |
Field effect transistor with narrow bandgap source and drain regions and
method of fabrication A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer... |
| US-9,614,060 |
Nanowire transistor with underlayer etch stops A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at... |
| US-9,613,934 |
Interconnect structures with polymer core Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit... |
| US-9,613,933 |
Package structure to enhance yield of TMI interconnections An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound... |
| US-9,613,920 |
Microelectronic package utilizing multiple bumpless build-up structures
and through-silicon vias A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second... |
| US-9,613,722 |
Method and apparatus for reverse memory sparing An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory... |
| US-9,613,698 |
Set and reset operation in phase change memory and associated techniques
and configurations Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an... |
| US-9,613,691 |
Apparatus and method for drift cancellation in a memory An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to:... |
| US-9,613,408 |
High dynamic range image composition using multiple images High dynamic range image composition is described using multiple images. Some embodiments relate to a system with a buffer to receive each of three different... |
| US-9,613,394 |
Lossy color compression using adaptive quantization Techniques related to graphics rendering including techniques for color compression and/or decompression using adaptive quantization are described. |
| US-9,613,294 |
Control of computer vision pre-processing based on image matching using
structural similarity A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in... |
| US-9,613,196 |
Protection system including machine learning snapshot evaluation This disclosure is directed to a protection system including machine learning snapshot evaluation. A device may comprise a machine learning engine (MLE) to... |
| US-9,613,001 |
Processing device for performing convolution operations Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a... |
| US-9,612,993 |
Dynamically configurable analog frontend circuitry An analog frontend (AFE) interface is dynamically programmable. A single AFE circuit can interface with multiple different analog devices, and dynamically... |
| US-9,612,986 |
High performance interconnect physical layer A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be... |
| US-9,612,979 |
Scalable memory protection mechanism An apparatus to protect contents of a memory region is presented. In one embodiment, the apparatus includes a non-volatile memory, memory check logic to... |
| US-9,612,951 |
Methods and apparatus to manage workload memory allocation Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and... |
| US-9,612,938 |
Providing status of a processing device with periodic synchronization
point in instruction tracing system In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic... |
| US-9,612,930 |
Providing autonomous self-testing of a processor In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch... |
| US-9,612,915 |
Flash memory-hosted local and remote out-of-service platform manageability A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer... |
| US-9,612,901 |
Memories utilizing hybrid error correcting code techniques Use of hybrid error correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether... |
| US-9,612,887 |
Firmware-related event notification This disclosure is directed to firmware-related event notification. A device may comprise an operating system (OS) configured to operate on a platform. During... |
| US-9,612,842 |
Coalescing adjacent gather/scatter operations According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first... |
| US-9,612,840 |
Method and apparatus for implementing a dynamic out-of-order processor
pipeline A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus... |
| US-9,612,835 |
MFENCE and LFENCE micro-architectural implementation method and system A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that... |
| US-9,612,833 |
Handling compressed data over distributed cache fabric Technologies are presented that optimize data processing cost and efficiency. A computing system may comprise at least one processing element; a memory... |
| US-9,612,794 |
Combined RF equalizer and I/Q imbalance correction Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a... |
| US-9,612,792 |
Dynamic adjustment of audio production Apparatuses, methods, and computer-readable media for dynamic configuration of audio production are described. Audio production nodes ("APNs") may produce... |
| US-9,612,652 |
Controlling power consumption by power management link Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power... |
| US-9,612,649 |
Method and apparatus to shutdown a memory channel A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter... |
| US-9,612,647 |
Power management for a physical layer interface connecting a display panel
to a display transmit engine By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various... |
| US-9,612,643 |
Controlling the CPU slew rates based on the battery state of charge Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes... |
| US-9,612,634 |
Apparatus, system and method for concealed venting thermal solution Some embodiments of an apparatus, system and method are described for a concealed venting thermal solution. An apparatus may comprise an enclosure arranged... |
| US-9,612,613 |
Current sensor based closed loop control apparatus A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to... |
| US-9,612,409 |
Hermetic sealing of optical module A hermetically sealable package may be formed from a top portion and a bottom portion mated along a seam at or near a plane of an optical fiber. A completed... |
| US-9,612,124 |
Navigation system and method with location-aware accuracy and/or power
adjustments In a navigation system and method, location-aware adjustments may be made to the accuracy and/or power of the navigation system by changing at least one setting... |
| US-9,612,060 |
Direct air impingement cooling of package structures Various embodiments of microelectronic package cooling assemblies are described. Those embodiments include a cooling assembly comprising an array of vertically... |
| US-9,611,372 |
Narrow-gap flip chip underfill composition An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight... |
| US-9,610,949 |
Individual driving preference adapted computerized assist or autonomous
driving of vehicles Apparatuses, methods and storage medium associated with computerized assist or autonomous driving (CA/AD) of vehicles are disclosed herein. In various... |
| US-9,609,782 |
Rack assembly structure Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may... |
| US-9,609,765 |
Chassis of electronic device A chassis for an electronic device may include a first metal layer to form an inner surface of the chassis, an insulating layer on the first metal layer, and a... |
| US-9,609,602 |
Always-on bearer for small data transfers in LTE systems When a UE in an LTE system enters the RRC_IDLE state, only the S5/S8 EPS bearer context is retained, and the S1-U, S1-AP and radio bearers are released. These... |
| US-9,609,585 |
Devices and method for cell search and detection A communication circuit arrangement may include a cell search circuit configured to compare a detected synchronization sequence of a detected candidate cell... |
| US-9,609,566 |
Radio resource control (RRC) protocol for integrated WLAN/3GPP radio
access technologies An integrated WLAN/WWAN Radio Access Technology (RAT) architecture is described in which signaling used to control the integration of the WLAN/WWAN architecture... |
| US-9,609,565 |
Mechanism to enable WiFi offload based on power preference of user
equipment In typical UEs, scanning for WiFi access points (APs) can consume a significant amount of power. This scanning occurs when the UE is connected through the... |
| US-9,609,564 |
Fast modulation and coding scheme adaptation protocol for long term
evolution with multiple-user multiple... Embodiments for providing fast modulation and coding scheme adaptation for LTE regardless of transmission using single-user multiple-input and multiple-output... |
| US-9,609,517 |
Cooperative security in wireless sensor networks Systems, apparatuses, and methods for cooperative security in wireless sensor networks are described herein. A wireless node may organize itself into a cluster... |
| US-9,609,502 |
Adaptive silencing mechanism for device-to-device (D2D) discovery Novel adaptive silencing schemes for device-to-device (D2D) discovery based on loading conditions in a discovery zone are disclosed herein. These adaptive... |
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