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Patent # Description
US-9,048,834 Grouping of physically unclonable functions
A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF...
US-9,048,824 Programmable equalization with compensated impedance
Described is a chip comprising: a pull-up driver with a first impedance, the pull-up driver coupled to a node; a pull-down driver with a second impedance, the...
US-9,048,789 Current re-using wideband low-noise active balun
Some aspects of the present disclosure relate to a low-noise amplifier (LNA) having a balun configuration. The LNA includes a DC current path coupling a first...
US-9,048,730 Switched mode power supply and a method for operating a switched mode power supply
A switched mode power supply provides a reduction of switching losses and increased efficiency. The switched mode power supply includes a first switch coupled...
US-9,048,314 Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
US-9,048,266 Apparatus and methods for improving parallel conduction in a quantum well device
Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments...
US-9,048,260 Method of forming a semiconductor device with tall fins and using hard mask etch stops
A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching...
US-9,048,084 Apparatus and method for extending bandwidth and supressing phase errors in multi-phase signals
Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a...
US-9,047,807 Device, system, and method of display calibration
Device, system, and method for display calibration. For example, an apparatus includes: one or more color sensors, embedded within a body of a mobile device, to...
US-9,047,491 Encryption acceleration
The subject matter herein relates to data processing and, more particularly, to encryption acceleration. Various embodiments herein provide devices and systems...
US-9,047,468 Migration of full-disk encrypted virtualized storage between blade servers
A method, system and computer-readable storage medium with instructions to migrate full-disk encrypted virtual storage between blade servers. A key is obtained...
US-9,047,417 NUMA aware network interface
Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented...
US-9,047,222 Unified multi-transport medium connector architecture
A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or...
US-9,047,204 Techniques to perform forward error correction for an electrical backplane
Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward...
US-9,047,187 Defect management in memory systems
Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a...
US-9,047,172 Adaptive power control of memory map storage devices
An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically...
US-9,047,171 Differentiating cache reliability to reduce minimum on-die voltage
Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory...
US-9,047,082 Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A...
US-9,047,081 Method, apparatus and instructions for parallel data conversions
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding...
US-9,047,066 Apparatus and method to efficiently cool a computing device
Embodiments disclosed herein include devices to cool the walls of a mobile computing device. In one embodiment, a louvered vent is formed within an external...
US-9,047,014 Frequency and voltage scaling architecture
A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the...
US-9,046,916 Cache prefetch for NFA instructions
Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA...
US-9,046,761 Lithography mask having sub-resolution phased assist features
Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or...
US-9,046,569 Seal method for direct liquid cooling of probes used at first level interconnect
Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments,...
US-9,046,552 On-die trim-able passive components for high volume manufacturing
Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order...
US-9,046,424 Throttling memory in a computer system
Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one...
US-9,044,172 Ergonomic detection, processing and alerting for computing devices
Methods, apparatuses and systems receive information, via at least one sensor, indicating an ergonomic characteristic of a user of a computing device. The...
US-9,043,773 Identification and management of unsafe optimizations
Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed...
US-9,043,681 Reconstructing codewords using a side channel
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel....
US-9,043,674 Error detection and correction apparatus and method
Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In...
US-9,043,665 Functional fabric based test wrapper for circuit testing of IP blocks
A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM...
US-9,043,659 Banking of reliability metrics
In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric...
US-9,043,649 Method and apparatus for output of high-bandwidth debug data/traces in ICS and SoCs using embedded high speed debug
Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from...
US-9,043,615 Method and apparatus for a trust processor
In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic...
US-9,043,604 Method and apparatus for key provisioning of hardware devices
Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure...
US-9,043,594 System and method for execution of a secured environment initialization instruction
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates...
US-9,043,583 Load/move and duplicate instructions for a processor
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first...
US-9,043,521 Technique for communicating interrupts in a computer system
A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is...
US-9,043,500 System and method for generating a virtual PCI-type configuration space for a device
An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information...
US-9,043,379 Method and apparatus for performing logical compare operation
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
US-9,043,133 Navigation systems and associated methods
Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a...
US-9,042,838 Transmit leakage cancellation in a wide bandwidth distributed antenna system
A system and methods for cancelling transmission leakage signals in a wide bandwidth Distributed Antenna System ("DAS") having remote units is disclosed. An...
US-9,042,696 Method and structure combining vertical and angled facets in silicon photonic waveguides
Embodiments of the invention use crystallographic etching of SOI wafers with a (110)-oriented epi layer to form both the vertical input facet and the re-entrant...
US-9,042,652 Techniques for connected component labeling
An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of...
US-9,042,599 Techniques for face detection and tracking
Techniques are disclosed that involve face detection. For instance, face detection tasks may be decomposed into sets of one or more sub-tasks. In turn the...
US-9,042,482 FBR DC vector offset removal using LO phase switching
One embodiment relates to a feedback receiver (FBR). The FBR includes a FBR signal input configured to receive a radio frequency (RF) signal, a first local...
US-9,042,468 Channel estimation technique
A method includes determining a sequence of first coefficient estimates of a communication channel based on a sequence of pilots arranged according to a known...
US-9,042,434 Filter
Method and filter for filtering a signal, in which the signal is applied to a delay line having a plurality of taps. Respective weighting coefficients of a...
US-9,042,429 Interference cancellation radio receiver
A radio receiver apparatus includes a serving cell detector configured to generate a detected serving cell signal based on a serving cell detector input signal....
US-9,042,400 Multi-detection of heartbeat to reduce error probability
A communications system improves performance of detecting a signal having an indication of a request to change communications states by making at least two...
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