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Packetizing JTAG across industry standard interfaces
Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors...
Memory allocation for virtual machines using memory map
Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality...
Non main CPU/OS based operational environment
A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based...
Optimizing energy efficiency using device idle duration information and
latency tolerance based on a pre-wake...
Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second...
Memory data inversion for reducing power consumption
Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
Symmetric key distribution framework for the Internet
A method, device, and system are disclosed. In one embodiment the method includes receiving measured health information from a client on a key distribution...
Booting an operating system of a system using a read ahead technique
In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the...
Processsor integral technologies for BIOS flash attack protection and
A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module...
Packing odd bytes from two source registers of packed data
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source...
Performing an atomic operation without quiescing an interconnect structure
In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This...
Multi-processor computing system having fast processor response to cache
agent request capacity limit warning
An apparatus is described that includes a plurality of processors, a plurality of cache slices and respective cache agents. Each of the cache agents have a...
Persistent log operations for non-volatile memory
In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information...
Controlling access to storage in a computing device
In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the...
Remote direct storage access
Embodiments of the present disclosure include systems, apparatuses, and methods that relate to remote, direct access of solid-state storage. In some...
Mobile platform tracking in wireless networks
A mobile station in a wireless network provides a presence indication when in a power saving state. The presence indication is sent periodically, and the period...
Location sensing using channel fading fingerprinting
A system and method are provided for providing precise location sensing for wireless devices in an indoor environment using channel fading fingerprinting. An...
Method and wireless transmit/receive unit (WTRU) for receiving multimedia
A method and wireless transmit/receive unit (WTRU) for receiving a multimedia broadcast/multicast service (MBMS) data is disclosed. A WTRU receives MBMS data...
Location processing in small cells implementing multiple air interfaces
A heterogeneous network which supports multiple communication technologies (e.g., communication in accordance with multiple air interface standards) in a...
Received signal to noise indicator
A method and device may be used to produce a received interference value in wireless communications. The device may include one or more components to measure a...
Dynamic switching frequency control of an on-chip or integrated voltage
Examples are disclosed for switching frequency control of an on-chip or integrated voltage regulator. In some examples, a switch frequency of an integrated...
Light receiver position determination
A light array includes lights that transmit modulated light to indicate their unique light identifiers (IDs) and lights that transmit unmodulated light. A light...
Analytics assisted encoding
Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions....
Method and apparatus for low-power AP-assisted fast wireless roaming using
optimized neighbor graphs
An embodiment of the present invention provides a method, comprising using optimized neighbor graphs for low-power access point assisted fast wireless roaming...
Multimode multicarrier modem system and method of communication over the
An alternative approach to coping with the ever increasing demand for faster communications hardware is to design modems that are capable of operating its...
Reducing the maximum latency of reserved streams
An embodiment may include circuitry that may facilitate, at least in part, assignment, at least in part, of at least one bandwidth reservation for at least one...
Apparatus, method and system of wireless communication according to a
protocol adaptation layer (PAL)...
A method and system may include a source station to provide wireless multicast transmission to a plurality of destination stations according to a protocol...
Routing of voice internet protocol packets to a selected processor
Methods and apparatuses for routing voice Internet Protocol (IP) packet to a selected processor are described herein. The methods may include initially...
Signaling for wireless communications
A communication system, such as a wireless CDMA system, detects markers with fewer errors by having field units transmit the markers at different power levels...
Network architecture for dual active personae cellular mobile devices
A communication device for providing dual-active personae using a single subscriber identification module. A long term evolution (LTE) protocol stack,...
Scheduling and hybrid automatic repeat request (HARQ) timing indication
for an uplink-downlink (UL-DL)...
Technology for reconfiguring an uplink-downlink (UL-DL) time-division duplexing (TDD) configuration timing is disclosed. In an example, a user equipment (UE)...
DRAM with pulse sense amp
Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and...
Charge storage device, method of making same, method of making an
electrically conductive structure for same,...
In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator...
Displaying data on lower resolution displays
Data intended to be displayed on a higher resolution display such as a non-interlaced display used as a computer monitor may be converted for display on a lower...
Adaptive virtual keyboard for handheld device
In various embodiments, the size, shape, and arrangement of keys on a virtual keyboard may be determined based on touchscreen contacts made by the user....
Method and apparatus for measuring audience size for a digital sign
Measuring audience size for a digital sign comprises generating a plurality of paths, one for each face detected in a first sequence of video frames captured by...
Digital fractional frequency divider
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a...
Method and apparatus for chip self deactivation
In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have...
Switched mode power supply and a method for operating a switched mode
A switched mode power supply provides a reduction of switching losses and increased efficiency. The switched mode power supply includes a first switch coupled...
Nanowire transistor devices and forming techniques
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within...
Combined optical and electrical interface
A connection port provides electrical and/or optical interface capability. The combined electrical and optical interface port may include an optical...
Magnetic attachment structure
The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic...
Processor having execution core sections operating at different clock
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section...
Platform-hardened digital rights management key provisioning
Embodiments of an invention for platform-hardened digital rights management key provisioning are disclosed. In one embodiment, a processor includes an execution...
Terminating enhanced television broadcasts
An enhanced television broadcast system may enable the transmission and reception of a real-time event when a new program is about to begin. The real-time event...
Speculative compilation to generate advice messages
Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with...
Type checking for object-oriented programming languages
Type checking between an object class and a target class may comprise getting an object header from an object, and checking from the object header a result of a...
Memory subsystem command bus stress testing
A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory...
Memory subsystem data bus stress testing
A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a...
Replacing blinded authentication authority
A manufacturing entity provides a blinded signature to a secure device and associates a time with the blinded signature. If a signing key is compromised, the...
Network storage target boot and network connectivity through a common
The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network...