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Pillar arrangement in NAND memory
Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the...
Recessed and embedded die coreless package
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a...
Self-aligned via and plug patterning with photobuckets for back end of
line (BEOL) interconnects
Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an...
Electrical interconnect for an electronic package
Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a...
Landside stiffening capacitors to enable ultrathin and other low-Z
Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an...
Register files including distributed capacitor circuit blocks
Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second...
Content adaptive LCD backlight control
An apparatus, computing device, and a computer readable medium are described herein. The apparatus includes logic to process pixels using content adaptive LCD...
Depth offset compression
Zmin and Zmax are determined for depth offset compression. Then a check determines whether Zmin is equal to Zmax. If so, only one of Zmin and Zmax is used for...
Always-available embedded theft reaction subsystem
A platform including an always-available theft protection system is described. In one embodiment, the system comprises an arming logic to arm the platform, when...
Techniques for adaptive interface support
Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in...
Delivering real time interrupts with an advanced programmable interrupt
Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced...
Early wake-warn for clock gating control
A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn...
Method and system for maintaining release consistency in shared memory
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in...
Test logic for a serial interconnect
An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages,...
SATA receiver equalization margin determination/setting method and
Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an...
Probabilistic flit error checking
A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic...
Functional unit for instruction execution pipeline capable of shifting
different chunks of a packed data...
A method is described that includes fetching an instruction. The method further includes decoding the instruction. The instruction specifies an operation, a...
Method and apparatus for performance efficient ISA virtualization using
dynamic partial binary translation
Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native...
Vector indexed memory access plus arithmetic and/or logical operation
processors, methods, systems, and...
A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is...
Apparatus and method for efficient memory renaming prediction using
A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a...
Apparatus, method and system for determining reference voltages for a
Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an...
Configuration information backup in memory systems
According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status...
Block partition to minimize power leakage
Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal...
Method, apparatus, and system for controlling power consumption of unused
hardware of a link interface
In an embodiment, a plurality of hardware buffers each may store information associated with one or more virtual channels. In turn, a configuration logic is to...
Constrained boot techniques in multi-core platforms
Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that...
Integrated and adjustable image projection with auto-image correction in
electronic devices using an in-facing...
A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or...
Current tests for I/O interface connectors
Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data...
High throughput biochemical detection using single molecule fingerprinting
Various embodiments provide devices, methods, and systems for high throughput biomolecule detection using transducer arrays. In one embodiment, a transducer...
Techniques for improved volumetric resistance blower apparatus, system and
Embodiments of an apparatus, system, method and techniques are described for an improved volumetric resistance blower and rotor. An apparatus may comprise, for...
Rotational to translational locking hinge
Techniques related to a hinge in a computing device are described herein. The techniques may include forming a shaft to move rotationally, and forming a sliding...
Stress buffer layer for integrated microelectromechanical systems (MEMS)
Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first...
Technologies for assisting vehicles with changing road conditions
Technologies for assisting vehicles with changing road conditions includes vehicle assistance data based on crowd-sourced road data received from a plurality of...
Network coverage hole detection
A technology for a user equipment (UE) that is operable to connect to a third generation partnership project (3GPP) long term evolution (LTE) cell in a cellular...
Blind decoding for an enhanced physical downlink control channel (EPDCCH)
Technology for a user equipment (UE) configured for blind decoding downlink control information (DCI) from an enhanced physical downlink control channel...
Power loading in MU-MIMO
Embodiments of a system and method for transmitting data from an access point in a multiple user multiple input multiple output (MU-MIMO) system are provided. A...
Geo-fence notification management
Embodiments for geo-fence notification management are generally described herein. A mobile device for geo-fence notification management may include a...
Wireless data transfer with improved transport mechanism selection
Generally, this disclosure describes devices, systems and methods for wireless data transfer with improved transport mechanism selection. The device may include...
Method and system of acoustic signal mixing
A system, article, and method of acoustic signal mixing comprises use of a total pair that is a count of the number of addition coefficients and subtraction...
Golden frame selection in video coding
Techniques related to designating golden frames and to determining frame sizes and/or quantization parameters golden and non-golden frames for video coding are...
Sensitive data tracking using dynamic taint analysis
A system and method for tracking sensitive data uses dynamic taint analysis to track sensitive data as the data flows through a target application running on a...
Backpressure techniques for multi-stream CAS
Techniques are disclosed for controlling data transmission in multi-stream digital systems. The techniques disclosed allow an input stream to a conditional...
Virtual multicarrier design for orthogonal frequency division multiple
Embodiments of the present invention provide a virtual multicarrier design for orthogonal frequency division multiple access communications. Other embodiments...
Apparatus for visible light communications in accordance with UFSOOK and
Embodiments may provide a way of communicating via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode...
Circuit, a time-to-digital converter, an integrated circuit, a
transmitter, a receiver and a transceiver
A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal...
Glitch-free digitally controlled oscillator code update
A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition...
Coarse tuning selection for phase locked loops
A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine...
Smart impedance matching for high-speed I/O
Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite...
Connector assembly for an electronic device
An electronic device includes an audio jack assembly that is to receive an audio input, wherein the audio jack assembly is provided concentrically with a...
Conductive oxide random access memory (CORAM) cell and method of
Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory...
Perpendicular MTJ stacks with magnetic anisotrophy enhancing layer and
crystallization barrier layer
Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy...