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Patent # Description
US-9,058,111 Read training a memory controller
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits...
US-9,058,106 Apparatus, system and method for context and language specific data entry
An apparatus, system and method that allow for context and language specific data entry via a user interface. A user interface is displayed on a display device,...
US-9,056,763 Stress buffer layer for integrated microelectromechanical systems (MEMS)
Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first...
US-9,055,594 Reducing transmission signal artifact spacing
A method of generating a transmission signal may include mixing a baseband signal assigned for transmission within a narrow frequency range ("assigned narrow...
US-9,055,533 Wireless communication device and method for improved WiFi and bluetooth coexistence usingreduced power for...
Disclosed in some examples is a method including receiving a downlink data packet over a first wireless link using a first wireless protocol during...
US-9,055,523 Apparatus, system and method of calibrating a radio delay of a wireless device
Some demonstrative embodiments include devices, systems and/or methods of calibrating a radio delay. For example, a radio delay calibrator may calibrate at...
US-9,055,477 Handling wait time in a congested wireless communication network
Embodiments of the present disclosure describe techniques and configurations for handling a wait time in a wireless communication network when the network is...
US-9,055,474 Apparatus for improved mobility in a wireless heterogeneous network
Generally, this disclosure provides apparatus and methods for improved User Equipment (UE) mobility in wireless heterogeneous networks. The UE device may...
US-9,055,315 System and method for providing integrated media
Methods and system deliver media to users of media presentation systems. In accordance with one embodiment of the invention, a media server communicates with a...
US-9,055,177 Content aware video resizing
In accordance with some embodiments, jitter accompanying video resizing, can be reduced or even eliminated by analyzing the content that is to be depicted and...
US-9,055,011 Methods and apparatus for linked-list circular buffer management
A buffer memory is provided that comprises a plurality of memory elements for storing data elements in an order of arrival, wherein the plurality of memory...
US-9,054,987 Single instruction processing of network packets
Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds...
US-9,054,938 Quadrature gain and phase imbalance correction
Generally speaking, methods and apparatuses which correct errors related to phase and gain imbalances in quadrature tuners are disclosed. The quadrature tuner...
US-9,054,933 Orthogonal frequency division multiplex (OFDM) receiver with phase noise mitigation and reduced latency
A system according to one embodiment includes a demodulator configured to receive an orthogonal frequency division multiplexed (OFDM) modulated signal...
US-9,054,925 Parallel digital-to-time converter architecture
This document discusses, among other things, digital-to-time converters (DTCs) and more particularly to parallel implementations of DTCs. In an example, an...
US-9,054,921 Method and apparatus for generating a plurality of modulated signals
A method and an apparatus provide a plurality of modulated signals by frequency shifting an output signal of a carrier signal generation circuit for obtaining a...
US-9,054,908 RFI mitigation using burst timing
A chip is provided to include a circuit to transmit one or more data bursts, where the circuit includes burst timing logic to insert gaps of a determined length...
US-9,054,902 Apparatus and system for switching equalization
Described herein is apparatus and system for switching equalization. The apparatus comprises a sampler to sample an input signal; and an attenuator, coupled to...
US-9,054,858 Transmission and detection in multiple-antenna transmission systems
An apparatus includes a transmit diversity encoder configured to use a block code of a length greater than one for encoding at least two consecutive symbols. A...
US-9,054,855 Synchronizing phases between local LO generation circuits
Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some...
US-9,054,769 Pre-processing unit for a signal processor
A pre-processing unit for a signal processor includes a pre-processing element. The pre-processing element is configured to receive data to be processed by the...
US-9,054,742 Error and erasure decoding apparatus and method
A codeword may have errors and erasures. In embodiments, an apparatus may include a syndrome calculator configured to generate partial syndromes of the...
US-9,054,720 System, apparatus and method to improve analog-to-digital converter output
According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output...
US-9,054,642 Systems and methods to provide compensated feedback phase information
A communication system includes a polar conversion component, a polar modulator, an RF front-end component, a feedback receiver, a delay compensation component,...
US-9,054,302 Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability...
US-9,054,215 Patterning of vertical nanowire transistor channel and gate with directed self assembly
Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical...
US-9,054,190 Methods of containing defects for non-silicon device engineering
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in...
US-9,054,178 Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate...
US-9,054,164 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to...
US-9,054,068 Etchstop layers and capacitors
Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense...
US-9,053,812 Fast exit from DRAM self-refresh
Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low...
US-9,053,550 Techniques for rapid stereo reconstruction from images
Stereo image reconstruction techniques are described. An image from a root viewpoint is translated to an image from another viewpoint. Homography fitting is...
US-9,053,523 Joint enhancement of lightness, color and contrast of images and video
In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then...
US-9,053,354 Fast face detection technique
A processor includes a face recognition block and a face detection block. The face detection block includes a scan block and control logic. The scan block may...
US-9,053,346 Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay...
A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical...
US-9,053,308 Multi electro-biometric user recognition
A pair of contacts on a processor-based device may be used to collect two different types of human physiological data. That data may then be used to...
US-9,053,267 Noise analysis using timing models
Various embodiments include apparatuses and methods to perform noise analysis on a circuit at a selected condition (e.g., process, voltage, and temperature)...
US-9,053,251 Providing a sideband message interface for system on a chip (SoC)
According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the...
US-9,053,244 Utilization-aware low-overhead link-width modulation for power reduction in interconnects
Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one...
US-9,053,059 Roots-of-trust for measurement of virtual machines
Embodiments of techniques and systems associated with roots-of-trust (RTMs) for measurement of virtual machines (VMs) are disclosed. In some embodiments, a...
US-9,053,042 Method, system, and device for modifying a secure enclave configuration without changing the enclave measurement
A system and method for adapting a secure application execution environment to support multiple configurations includes determining a maximum configuration for...
US-9,053,040 Filtering mechanism for render target line modification
Modification messages may be filtered to reduce the load on a message channel between a render cache and a frame buffer compression. A group of cache lines may...
US-9,053,025 Apparatus and method for fast failure handling of instructions
A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the...
US-9,053,022 Synchronous software interface for an accelerated compute engine
Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous...
US-9,053,014 Repurposing NAND ready/busy pin as completion interrupt
A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy...
US-9,052,985 Method and apparatus for efficient programmable cyclic redundancy check (CRC)
A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data...
US-9,052,947 Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a...
US-9,052,902 Techniques to transmit commands to a target device to reduce power consumption
Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands...
US-9,052,901 Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum...
An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a...
US-9,052,899 Idle power reduction for memory subsystems
Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention...
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