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Patent # Description
US-9,040,237 Sensor arrays and nucleic acid sequencing applications
Embodiments of the present invention provide devices methods for sequencing DNA using arrays of reaction cavities containing sensors to monitor changes in...
US-9,038,034 Compiling for programmable culling unit
During compilation, the interval bounds for a programmable culling unit are calculated if possible. For each variable, interval bounds are calculated during the...
US-9,037,991 Apparatus and method for digital content navigation
An electronic device includes a processor, a memory for storing digital content and a display. The processor forms a content navigation bar for the digital...
US-9,037,943 Identification of non-volatile memory die for use in remedial action
Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile...
US-9,037,903 Apparatus and method for partial memory mirroring
An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core...
US-9,037,889 Apparatus and method for determining the number of execution cores to keep active in a processor
A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number...
US-9,037,887 Energy-efficient application content update and sleep mode determination
Embodiments of methods, systems, and storage medium associated with are disclosed herein. In one instance, the method may include: first determining whether the...
US-9,037,885 Independent power control of processing cores
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least...
US-9,037,883 Apparatus, method, and system for improved power delivery performance with a dynamic voltage pulse scheme
An apparatus and method is described herein for providing a dynamic pulse scheme for a voltage supply. A load (current) demand event of a processor is either...
US-9,037,869 Delivering data from a secure execution environment to a display controller
Methods and systems may include a computing system having a display, a display controller with a decryption module, and a security element with security logic....
US-9,037,840 Mechanism to provide workload and configuration-aware deterministic performance for microprocessors
An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is...
US-9,037,823 Protecting IAT/EAT hooks from rootkit attacks using new CPU assists
The present disclosure provides systems and methods for hardware-enforced protection from malicious software. A device may include at least a security validator...
US-9,037,820 Optimized context drop for a solid state drive (SSD)
A mass storage system employs a paging table for memory page redirection and maintains the paging table for power loss recovery (PLR) using a FIFO queue of...
US-9,037,812 Method, apparatus and system for memory validation
Techniques and mechanisms for assuring that one or more addressable locations in memory of a computer platform are transitioned from potentially invalid state...
US-9,037,804 Efficient support of sparse data structure access
Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field...
US-9,037,761 Configurable buffer allocation for multi-format video processing
Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with...
US-9,037,688 System having trace resources
A system includes a functional unit having a plurality of components. The system further includes trace resources for tracking processes executed by the...
US-9,037,627 Method and apparatus for performing logical compare operations
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
US-9,037,626 Method and apparatus for performing logical compare operations
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
US-9,037,408 Systems and methods for providing variable position precision
Systems and methods that provide positional data with a variable level of precision may be implemented on positional systems of electronic devices by...
US-9,037,397 System and method for generating alternative routes
A system and method for generating routes is provided. Weights may be computed and associated with route segments. A start and end point may be received. At...
US-9,037,099 Techniques to manage channel prediction
A system, apparatus, method and article to manage channel prediction for a wireless communication system are described. The apparatus may include a media access...
US-9,037,091 Transmission of channel quality data in wireless communication systems
Briefly, in accordance with one or more embodiments, data transmitted from a transmitter is received in a downlink channel, and channel quality data is fed back...
US-9,036,954 Optical waveguide structure
Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device...
US-9,036,728 Group resource allocation techniques for IEEE 802.16M
Group resource allocation techniques for IEEE 802.16m are generally presented. In this regard a method is introduced comprising generating a plurality of...
US-9,036,718 Low speed access to DRAM
Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may...
US-9,036,603 Network assistance for device-to-device discovery
Embodiments of system and method configurations for device discovery and connection establishment in connection with use of device-to-device (D2D) and...
US-9,036,473 Control and data plane solutions for carrier-aggregation based WLAN offload
Systems and methods for controlling data traffic offload to a WLAN (e.g., a Wi-Fi network) from a WWAN (e.g., a 4G LTE network) are generally disclosed herein....
US-9,036,047 Apparatus and techniques for image processing
An apparatus may include an image sensor that contains a multiplicity of pixel elements to detect one or more images and a processor circuit coupled to the...
US-9,035,962 Technique to share information among different cache coherency domains
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches...
US-9,035,960 Technique to share information among different cache coherency domains
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches...
US-9,035,959 Technique to share information among different cache coherency domains
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches...
US-9,035,686 Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first...
US-9,035,627 Switched mode power supply employing first and second feedback signals and a method of operating thereof
A switched mode power supply includes a first switch, a second switch, an inductor, an output capacitor, and a driving circuit for driving the first switch and...
US-9,035,387 Multi-gate device
Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
US-9,035,194 Circuit board with integrated passive devices
Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and...
US-D729,791 At least partially transparent input device for an electronic computer
US-9,032,493 Connecting mobile devices, internet-connected vehicles, and cloud services
A three-way trust relationship is established between a mobile device, Internet-connected vehicle system, and a cloud-based service. Access rights are granted...
US-9,032,428 Validation of TV viewership utilizing methods, systems and computer control logic
A method, system and computer control logic to provide personalization of a viewer's usage of an Internet TV platform. The method includes tracking a viewer's...
US-9,032,381 State recovery methods and apparatus for computing platforms
State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to...
US-9,032,246 Redundant file storage system with parity information
Some embodiments of the invention shift the responsibility for creating parity and error correction blocks from the hardware or software RAID units or modules...
US-9,032,232 Instruction for enabling a processor wait state
In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a...
US-9,032,226 Providing per core voltage and frequency control
In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a...
US-9,032,225 Determination of wake signal initiation on shared wake pins in computing devices
Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device...
US-9,032,223 Techniques to manage operational parameters for a processor
Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical...
US-9,032,139 Memory allocation for fast platform hibernation and resumption of computing systems
Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented...
US-9,032,137 Flexible wear management for non-volatile memory
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems...
US-9,032,126 Increasing turbo mode residency of a processor
In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of...
US-9,032,125 Increasing turbo mode residency of a processor
In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of...
US-9,032,105 Scalable method and apparatus to configure a link
Disclosed herein axe reconfigurable ports and methods for doing the same.
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