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Patent # Description
US-9,438,265 Phase multiplexer
Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described...
US-9,438,259 Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for generating a processed...
A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal...
US-9,438,219 Hybrid digital pulse width modulation (PWM) based on phases of a system clock
Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), ...
US-9,438,179 Amplifier apparatus and soft-start method thereof
An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and...
US-9,438,178 Mixer impairment correction based on volterra series
Techniques for compensating for signal impairments introduced by a mixer are discussed. One example system employing such techniques can include mixer...
US-9,438,172 Digital multi-level envelope tracking for wide-bandwidth signals
Digital envelope tracking with multilevel supply voltages is performed for wide-bandwidth signals. A digital control component generates a digital control code...
US-9,437,934 Device including reflective element to reflect directional wireless signals impinging thereon in a direction...
A computing device includes a body, the body having a first and second portion. The computing device further includes a directional antenna, the directional...
US-9,437,808 Electric field enhanced spin transfer torque memory (STTM) device
Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer...
US-9,437,710 Method for improving transistor performance through reducing the salicide interface resistance
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a...
US-9,437,706 Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal...
A microelectronic device may be formed with at least one transistor having a source region and a drain region, wherein an interlayer dielectric layer may be...
US-9,437,691 Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced...
US-9,437,569 High density substrate routing in BBUL package
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
US-9,437,546 Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
US-9,437,545 Interconnects having sealing structures to enable selective metal capping layers
Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an...
US-9,437,468 Heat assisted handling of highly warped substrates post temporary bonding
A heated non-contact wafer handling gripper may heat a thin device wafer bottom surface having a temporary bonding adhesive residue after debonding of the...
US-9,437,298 Self-storing and self-restoring non-volatile static random access memory
An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated...
US-9,437,293 Integrated setback read with reduced snapback disturb
Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus...
US-9,437,201 Advanced watermarking system and method
A method, computer program product, and computing device for obtaining an uncompressed digital media data file. One or more default watermarks is inserted into...
US-9,437,001 Tracking objects in bowl-shaped imaging systems
Technologies for determining a distance of an object from a vehicle include a computing device to identify an object captured in a fisheye image generated by a...
US-9,436,982 Scalable rank filter
A scalable rank filter and method for performing rank filtering are disclosed. In one embodiment, the rank filter comprises a W staged pipeline with W stages to...
US-9,436,972 System coherency in a distributed graphics processor hierarchy
Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one...
US-9,436,931 Remote prompting infrastructure
The invention relates to a method and apparatus for sending and receiving prompts to end-users inside and outside the home. A prompt, for example, a message,...
US-9,436,847 Cryptographic pointer address encoding
A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g.,...
US-9,436,839 Tokenization using multiple reversible transformations
Technologies for tokenizing data including a computing device to extract plaintext data from an input file to be tokenized. The computing device performs data...
US-9,436,838 Secure local web application data manager
Apparatus, systems and methods may provide a browser interface to detect an attempt by web content to manipulate data in a local data store. In addition, the...
US-9,436,819 Securely pairing computing devices
In an embodiment, an apparatus comprises a secure storage to store an entry having an identifier of a device to be paired with the apparatus and a master key...
US-9,436,812 Platform-hardened digital rights management key provisioning
Embodiments of an invention for platform-hardened digital rights management key provisioning are disclosed. In one embodiment, a processor includes an execution...
US-9,436,651 Method and apparatus for managing application state in a network interface controller in a high performance...
Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a...
US-9,436,632 Accessing data stored in a command/address register device
A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by...
US-9,436,623 Run-time fabric reconfiguration
Methods, apparatus and systems for implementing run-time fabric reconfiguration are described herein. In accordance with one aspect, techniques are disclosed...
US-9,436,622 Broadcasting communications over an advertising channel
Apparatuses, methods and storage media for communications between a peripheral device and host device in the absence of established connection between the...
US-9,436,605 Cache coherency apparatus and method minimizing memory writeback operations
An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation...
US-9,436,576 Methods, systems and apparatus to capture error conditions in lightweight virtual machine managers
Methods and apparatus are disclosed to capture error conditions in lightweight virtual machine managers. A disclosed example method includes defining a shared...
US-9,436,469 Methods to optimize a program loop via vector instructions using a shuffle table and a mask store table
According to one embodiment, a code optimizer is configured to receive first code having a program loop implemented with scalar instructions to store values of...
US-9,436,468 Technique for setting a vector mask
A technique to generate a vector mask. In particular, at least one embodiment of the invention matches at least two instructions used in generating a vector...
US-9,436,435 Apparatus and method for vector instructions for large integer arithmetic
An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic...
US-9,436,433 Method, apparatus and instructions for parallel data conversions
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding...
US-9,436,431 Anonymously tailoring environments to the preferences of physically proximate users
Systems and methods may detect a proximity of one or more client devices to a venue that provides ambient music and generate an anonymous playlist based on...
US-9,436,295 Alternate dynamic keyboard for convertible tablet computers
Systems and methods may provide for detecting an event on a computing device having an embedded keyboard with a default mapping of keys to functions and...
US-9,436,269 Automatically adjusting display areas to reduce power consumption
In an embodiment, a method includes receiving user interface information having event registrations for a user interface to be displayed on a display of a...
US-9,436,262 Mobile systems with seamless transition by activating second subsystem to continue operation of application...
A computer system includes two or more subsystems. In one example, a first subsystem is executing a multimedia application using data stored in a first storage...
US-9,436,254 Method and apparatus for per core performance states
A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at...
US-9,436,251 Fast platform hibernation and resumption of computing systems
Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a...
US-9,436,245 Dynamically computing an electrical design point (EDP) for a multicore processor
In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core...
US-9,436,244 Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O...
Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are...
US-9,436,240 Electronic device having an active edge
An electronic device is provided that includes a base, a processor, and a tablet having a front surface, a rear surface and a bottom edge surface. A processor...
US-9,435,967 Optical connection techniques and configurations
Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for...
US-9,435,655 Coordinated crowd dispersal navigation
Various systems and methods for coordinating crowd dispersal are described herein. A system for coordinating crowd dispersal includes a user module to: identify...
US-9,434,135 Panel with releasable core
Generally discussed herein are systems and apparatuses that can include a releasable core panel. The disclosure also includes techniques of making and using the...
US-9,434,029 High performance transient uniform cooling solution for thermal compression bonding process
Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro...
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