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Frequency and voltage scaling architecture
A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the...
Cache prefetch for NFA instructions
Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA...
Lithography mask having sub-resolution phased assist features
Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or...
Seal method for direct liquid cooling of probes used at first level
Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments,...
On-die trim-able passive components for high volume manufacturing
Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order...
Throttling memory in a computer system
Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one...
Ergonomic detection, processing and alerting for computing devices
Methods, apparatuses and systems receive information, via at least one sensor, indicating an ergonomic characteristic of a user of a computing device. The...
Identification and management of unsafe optimizations
Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed...
Reconstructing codewords using a side channel
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel....
Error detection and correction apparatus and method
Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In...
Functional fabric based test wrapper for circuit testing of IP blocks
A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM...
Banking of reliability metrics
In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric...
Method and apparatus for output of high-bandwidth debug data/traces in ICS
and SoCs using embedded high speed debug
Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from...
Method and apparatus for a trust processor
In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic...
Method and apparatus for key provisioning of hardware devices
Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure...
System and method for execution of a secured environment initialization
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates...
Load/move and duplicate instructions for a processor
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first...
Technique for communicating interrupts in a computer system
A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is...
System and method for generating a virtual PCI-type configuration space
for a device
An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information...
Method and apparatus for performing logical compare operation
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
Navigation systems and associated methods
Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a...
Transmit leakage cancellation in a wide bandwidth distributed antenna
A system and methods for cancelling transmission leakage signals in a wide bandwidth Distributed Antenna System ("DAS") having remote units is disclosed. An...
Method and structure combining vertical and angled facets in silicon
Embodiments of the invention use crystallographic etching of SOI wafers with a (110)-oriented epi layer to form both the vertical input facet and the re-entrant...
Techniques for connected component labeling
An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of...
Techniques for face detection and tracking
Techniques are disclosed that involve face detection. For instance, face detection tasks may be decomposed into sets of one or more sub-tasks. In turn the...
FBR DC vector offset removal using LO phase switching
One embodiment relates to a feedback receiver (FBR). The FBR includes a FBR signal input configured to receive a radio frequency (RF) signal, a first local...
Channel estimation technique
A method includes determining a sequence of first coefficient estimates of a communication channel based on a sequence of pilots arranged according to a known...
Method and filter for filtering a signal, in which the signal is applied to a delay line having a plurality of taps. Respective weighting coefficients of a...
Interference cancellation radio receiver
A radio receiver apparatus includes a serving cell detector configured to generate a detected serving cell signal based on a serving cell detector input signal....
Multi-detection of heartbeat to reduce error probability
A communications system improves performance of detecting a signal having an indication of a request to change communications states by making at least two...
Communication device and method for transmitting data
Embodiments of the invention relate generally to communication devices and to a method for transmitting data. In an embodiment of the invention, a communication...
Beamforming using base and differential codebooks
Embodiments of methods and apparatus for determining and/or quantizing a beamforming matrix are disclosed. In some embodiments, the determining and/or...
Techniques for evaluation and improvement of user experience for
applications in mobile wireless networks
Techniques are described for evaluating and improving a user experience for applications in mobile wireless networks. In some embodiments, for example, traffic...
Reducing wireless power consumption and signaling overhead for internet
application background messages
Technology is discussed for reducing the frequency of signaling overhead and power consumption on wireless mobile devices employed to support internet...
User equipment with reduced power consumption operational modes
A user equipment (UE) power-cycles UE transmission modem components to reduce overall UE power consumption. For example, multiple HARQ ACK/NACK feedback bits...
Minimizing power consumption in a network device
A network interface device (NID) may determine whether the received data units of the computer system are to be compressed before transmitting the data units....
Using a reference bit line in a memory
Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line...
Charge pump redundancy in a memory
An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of...
Mechanism for employing and facilitating an edge thumb sensor at a
A mechanism is described for employing and facilitating a thumb sensor at a computing device. A method of embodiments of the invention includes extending a...
Circuit and method
Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a...
Context aware detection and mobile platform wake
A device includes a processor having a standby state, a control unit coupled to the processor to receive wireless identification information, and a storage...
The adjustable resonator according to the invention has a casing, which is composed of walls, a lid and a bottom, a resonator cavity inside the casing and an...
Circuit arrangement with a plurality of on-chip monitor circuits and a
control circuit and corresponding methods
Implementations are presented herein that include a plurality of on-chip monitor circuits and a controller. Each of the plurality of on-chip monitor circuits is...
Battery charge management using a scheduling application
According to some embodiments, battery charge management using a scheduling application is disclosed. A first parameter may be received from a scheduling...
Self-aligned via patterning with multi-colored photobuckets for back end
of line (BEOL) interconnects
Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for...
Method to increase I/O density and reduce layer counts in BBUL packages
An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of...
Reliable microstrip routing for electronics components
A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization...
Logic chip including embedded magnetic tunnel junctions
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a...
Three-dimensional germanium-based semiconductor devices formed on globally
or locally isolated substrates
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device...
Mechanical adhesion of copper metallization to dielectric with partially
cured epoxy fillers
In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a...