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Patent # Description
US-9,087,037 Functional fabric based test access mechanism for SoCs
A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test...
US-9,087,000 Accessing private data about the state of a data processing machine from storage that is publicly accessible
According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written...
US-9,086,966 Systems, apparatuses, and methods for handling timeouts
Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training...
US-9,086,958 Maintaining processor resources during architectural events
In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second...
US-9,086,913 Processor extensions for execution of secure embedded containers
Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for...
US-9,086,893 Techniques to store configuration information in an option read-only memory
Method and apparatus to store configuration information in an option read-only memory are described.
US-9,086,881 Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions...
A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one...
US-9,086,873 Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture
Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are...
US-9,086,872 Unpacking packed data in multiple lanes
Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first...
US-9,086,852 Fastening techniques for electronic devices
A computing device including fastening features. The computing device may include an upper shell comprising an upper boss protruding from the upper shell, the...
US-9,086,834 Controlling configurable peak performance limits of a processor
In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum...
US-9,086,823 Providing adaptive frequency control for a processor using utilization information
In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an...
US-9,085,461 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode...
US-9,084,260 Systems for communicating using multiple frequency bands in a wireless network
Communication signals using a first and a second frequency band in a wireless network is described herein. The first frequency band may be associated with a...
US-9,084,123 Radio communication devices and methods for controlling a radio communication device
A radio communication device may be provided. The radio communication device may include: a measurement circuit configured to measure a reception quality of a...
US-9,084,081 Mobile device and method for automatic connectivity, data offloading and roaming between networks
Embodiments of a mobile device and methods automatically connecting to a Wi-Fi Hotspot 2.0 are generally described herein. In some embodiments, subscription...
US-9,083,959 Real-time automatic conversion of 2-dimensional images or video to 3-dimensional stereo images or video
Systems, apparatus and methods are described related to real-time automatic conversion of 2-dimensional images or video to 3-dimensional stereo images or video.
US-9,083,775 ANDSF policies for WLAN and PLMN selection
In embodiments, a user equipment (UE) may be able to identify one or more access network discovery and selection function (ANDSF) policies which the UE can use...
US-9,083,768 Content sharing device management
Computer-readable storage medium, apparatus and method associated with sharing content between users of a computing environment are disclosed herein. In...
US-9,083,617 Reducing latency of at least one stream that is associated with at least one bandwidth reservation
An embodiment may include circuitry to determine, at least in part, whether to delay transmission, at least in part, of at least one frame in favor of...
US-9,083,479 Signaling for downlink coordinated multipoint in a wireless communication system
Embodiments herein describe apparatuses, systems, and methods for signaling to support downlink coordinated multipoint (CoMP) communications with a user...
US-9,083,416 Combining in receive diversity systems
A receiver apparatus includes a first receiver having an input for receiving a first version of a signal received by a first receive antenna. The receiver...
US-9,083,403 Multiple input, multiple output wireless communication system, associated methods and data structures
Briefly, in accordance with one or more embodiments, a wireless signal is transmitted to a remote device. The remote device determines a precoding matrix...
US-9,083,378 Dynamic compression/decompression (CODEC) configuration
The present disclosure is directed dynamic compression/decompression (codec) configuration. In general, a device may include a codec configuration module to...
US-9,083,377 Analog-to-digital converter
A technique includes receiving an analog signal and generating at least one second signal that has a timing indicative of a magnitude of the analog signal. The...
US-9,083,284 Wide-band multi stage Doherty power amplifier
A multi-stage Doherty power amplifier ("PA") circuit which achieves superior efficiency over broadband range of frequencies is disclosed. Conventional...
US-9,083,073 Thin chassis near field communication (NFC) antenna integration
Described herein are techniques related one or more systems, apparatuses, methods, etc. for integrating a near field communications (NFC) coil antenna in a...
US-9,082,714 Use of etch process post wordline definition to improve data retention in a flash memory device
Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device....
US-9,082,509 Method and apparatus for reading variable resistance memory elements
In some embodiments, detecting resistance in a resistive memory cell may be done using a pulse edge. For example, a pulse may be applied through a resistive...
US-9,082,347 Illumination modulation technique for microdisplays
A projection display may use pulse width modulation wherein the duty cycle may be varied. This duty cycle variation may improve bit depth in some embodiments....
US-9,082,228 Analytical motion blur rasterization with compression
A rasterizer, based on time-dependent edge equations, computes analytical visibility in order to render accurate motion blur. An oracle-based compression...
US-9,082,111 Method and apparatus for dynamically processing events based on automatic detection of time conflicts
A scheduling apparatus, system, and article including a machine-accessible medium, along with a method of dynamically processing events, are disclosed. The...
US-9,081,954 Verifying firmware integrity of a device
In one embodiment, the present invention includes a method for receiving an integrity request in a device of a computer system from a software entity external...
US-9,081,947 Turing test based user authentication and user presence verification system, device, and method
A password-less method for authenticating a user includes capturing one or more images of a face of the user and comparing the one or more images with a...
US-9,081,940 Method and service for user transparent certificate verifications for web mashups and other composite applications
Embodiments for providing user transparent certificate verifications for web mashups and other composite applications are generally described herein. In some...
US-9,081,786 Systems and methods for creating self-extracting files
Systems and methods are disclosed for creating a self-extracting file from any given input file type with minimum user interaction. The systems and methods...
US-9,081,742 Network communications processor architecture
Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core...
US-9,081,709 Virtualizable and forward-compatible hardware-software interface
Methods and apparatus are disclosed for virtualizable, forward-compatible hardware-software interfaces. Embodiments may be used in a driver whether it is a...
US-9,081,707 Apparatus and method for tracking TLB flushes on a per thread basis
A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining...
US-9,081,688 Obtaining data for redundant multithreading (RMT) execution
In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block...
US-9,081,687 Method and apparatus for MONITOR and MWAIT in a distributed cache architecture
A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR...
US-9,081,628 Detecting potential access errors in a multi-threaded application
In one embodiment, a method includes maintaining thread analysis metadata for a multi-threaded application. The metadata may include a thread vector clock for...
US-9,081,577 Independent control of processor core retention states
In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first...
US-9,081,575 Method and apparatus for a zero voltage processor sleep state
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to...
US-9,081,573 Method and apparatus for automatically repainting an external display during transitioning to a low power state
A computer system may include a main display and an external display coupled, for example, to the computer system through a universal serial bus digital visual...
US-9,081,562 Unpacking packed data in multiple lanes
Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first...
US-9,081,557 Dynamically allocating a power budget over multiple domains of a processor
In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining...
US-9,081,554 Heat exchanger assembly for electronic device
In one embodiment a heat exchanger assembly comprises at least one heat pipe and a casing which is to receive a blower, the casing comprising a plurality of...
US-9,078,766 Device and method with power efficient location notification function by periodically deactivating signal-based...
Before a device enters a power saving mode, a location-aware application in the device may provide at least one wake trigger (and a trigger limit) to a low...
US-9,078,271 Techniques to train a personal area network component
Techniques to train a personal area network component may include obtaining a packet error rate from a personal area network component. It may be determined...
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