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Patent # Description
US-9,767,235 Method and device for the design of thermal models for electronic systems
The invention relates to a method and device for thermal simulation of electronic systems involving breaking down the system into parts being in a single...
US-9,767,064 Low power universal serial bus
Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer...
US-9,767,044 Secure memory repartitioning
Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and...
US-9,767,042 Enhancing cache performance by utilizing scrubbed state indicators associated with cache entries
Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may...
US-9,767,041 Managing sectored cache
Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to...
US-9,767,038 Systems and methods for accessing a unified translation lookaside buffer
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one...
US-9,767,037 Technologies for position-independent persistent memory pointers
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing...
US-9,767,026 Providing snoop filtering associated with a data buffer
In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip...
US-9,767,024 Cache closure and persistent snapshot in dynamic code generating system software
Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation...
US-9,767,020 Systems and methods for faster read after write forwarding using a virtual address
Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from...
US-9,766,999 Monitoring performance of a processing device to manage non-precise events
In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise...
US-9,766,997 Monitoring performance of a processor using reloadable performance counters
In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor...
US-9,766,979 Error correction in solid state drives (SSD)
A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less...
US-9,766,971 Physical layer device operation system and method
Apparatuses, systems and methods associated with causing a physical layer (PHY) device are disclosed herein. In embodiments, an apparatus may include a memory...
US-9,766,968 Byte level granularity buffer overflow detection for memory corruption detection architectures
Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a...
US-9,766,963 Secure tunneling access to debug test ports on non-volatile memory storage units
Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug...
US-9,766,897 Method and apparatus for integral image computation instructions
A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by...
US-9,766,893 Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a...
US-9,766,892 Method and apparatus for efficient execution of nested branches on a graphics processor unit
An apparatus and method for executing nested control flow instructions on a graphics processing unit (GPU). For example, one embodiment of a processor...
US-9,766,891 Apparatus, system, and method for persistent user-level thread
Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and...
US-9,766,889 Memory management in secure enclaves
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution...
US-9,766,888 Processor instruction to store indexes of source data elements in positions representing a sorted order of the...
A processor of an aspect includes packed data registers, and a decode unit to decode an instruction. The instruction may indicate a first source packed data to...
US-9,766,887 Multi-register gather instruction
A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand...
US-9,766,886 Instruction and logic to provide vector linear interpolation functionality
Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a...
US-9,766,827 Apparatus for data retention and supply noise mitigation using clamps
An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power...
US-9,766,817 Read training a memory controller
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits...
US-9,766,814 Method and apparatus for defect management in a non-volatile memory device
Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes...
US-9,766,701 Display dimming in response to user
In some embodiments a detector is to detect a body of a user. A controller is to determine an area of focus of the user in response to the detector, and to dim...
US-9,766,700 Gaze activated content transfer system
A gaze activated data unit transfer system is described. An apparatus may comprise a gaze interface application operative on a processor circuit to manage data...
US-9,766,685 Controlling power consumption of a processor using interrupt-mediated on-off keying
In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a...
US-9,766,683 Interconnect to communicate information uni-directionally
A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to...
US-9,766,678 Multiple voltage identification (VID) power architecture, a digital synthesizable low dropout regulator, and...
Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external...
US-9,766,676 Computing subsystem hardware recovery via automated selective power cycling
Various embodiments are generally directed to automated selective power cycling of an inoperative hardware-based subsystem of a computing device, while not...
US-9,766,675 Methods and apparatuses to provide power in idle states
A load associated with one or more components coupled via one or more ports to a first power supply rail is monitored. The one or more components are switched...
US-9,766,674 USB power delivery controller sharing
A system for sharing a power delivery controller is described herein. The system includes a plurality of ports and a power delivery controller communicatively...
US-9,766,673 Supercapacitor-based power supply protection for multi-node systems
In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the...
US-9,766,672 System for managing power provided to a processor or memory based on a measured memory consumption characteristic
In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic...
US-9,766,665 Multiple mode display apparatus
A multiple mode display apparatus and methods of use. An apparatus includes a display surface with a first and a second display area. A housing pivotally...
US-9,766,661 Stacking detachable tablet
Particular embodiments described herein provide for an electronic device that could include a circuit board coupled to a plurality of electronic components...
US-9,766,276 Power adapter detection
A method and system are described herein for detecting a capacity for a power adapter. An example of a method includes detecting an increase in power...
US-9,766,121 Mobile device based ultra-violet (UV) radiation sensing
The present application discloses device and system embodiments that address mobile device integration considerations for various categories of UV sensors,...
US-9,765,439 Electroplated plastic chassis for electronic device
In one example an electronic device comprises a controller and a chassis comprising a polymer layer, a first metallic layer deposited on a first side of the...
US-9,763,364 Heat transfer liquid flow method and apparatus
Apparatus and method to facilitate heat transfer fluid flow are disclosed herein. A flexible tube having first and second ends facilitates a heat transfer fluid...
US-9,763,266 Systems and methods for scheduling wireless communication
Provided are systems and methods for a network station identifying a communication schedule announced by a first wireless network station, determining that the...
US-9,763,254 Arrangements for association and re-association in a wireless network
A method is disclosed for associating network devices to a network. The method can include receiving a beacon from a source by an antenna array, allocating...
US-9,763,238 Signaling uplink frame duration in wireless local-area networks
Computing readable media, apparatuses, and methods for signaling UL frame duration in wireless local-area networks. An apparatus of a wireless device is...
US-9,763,235 Paging repetition for increased robustness for extended paging cycles
Embodiments described herein relate generally to a reliable delivery of a paging message in a wireless network environment. To prevent the unacceptable delay of...
US-9,763,210 Evolved node-B and user equipment and methods for operation in a coverage enhancement mode
Embodiments of an eNB to operate in accordance with a coverage enhancement mode are disclosed herein. The eNB may comprise hardware processing circuitry to,...
US-9,763,128 Measurement reporting in D2D communication
An apparatus is provided for use in a User Equipment, UE, comprising an input to receive an information element, IE, during a device-to-device, D2D,...
US-9,763,127 User equipment handover error reporting
Embodiments described herein relate generally to a user equipment ("UE") that is to transmit a handover error report to an access node. An access node may use...
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