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Patent # Description
US-1,016,3502 Selective performance level modes of operation in a non-volatile memory
In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a...
US-1,016,3500 Sense matching for hard and soft memory reads
Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For...
US-1,016,3471 Time tracking with trits
A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global...
US-1,016,3468 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction...
US-1,016,3320 Technologies for determining a threat assessment based on fear responses
Technologies for determining a threat assessment based on fear responses comprises monitoring sensor data received from a sensor array located at a monitored...
US-1,016,3187 Graphics rendering using a hierarchical acceleration structure
A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d...
US-1,016,3179 Method and apparatus for intelligent cloud-based graphics updates
An apparatus and method are described for cloud-based graphics updates. For example, one embodiment of an apparatus comprises a system optimization agent to...
US-1,016,3087 Systems and method for selling content over a network
A method to generate revenue from supplied content is provided. Content is provided to a consumer via a network by providing a content service that allows the...
US-1,016,2842 Data partition and transformation methods and apparatuses
Apparatuses, methods and storage medium associated with processing data are disclosed herewith. In embodiments, an apparatus may include a data pre-processor to...
US-1,016,2770 Virtual machine migration in rack scale systems
Virtual machine (VM) migration in rack scale systems is disclosed. A source shared memory controller (SMC) of implementations includes a direct memory access...
US-1,016,2758 Opportunistic increase of ways in memory-side cache
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of...
US-1,016,2756 Memory-efficient last level cache architecture
A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level...
US-1,016,2750 System address reconstruction
System address reconstruction logic in accordance with one embodiment of the present description, reconstructs a system address from a channel address...
US-1,016,2694 Hardware apparatuses and methods for memory corruption detection
Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an...
US-1,016,2687 Selective migration of workloads between heterogeneous compute elements based on evaluation of migration...
A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher...
US-1,016,2640 Instruction for performing an overload check
A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether...
US-1,016,2639 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality...
US-1,016,2638 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality...
US-1,016,2637 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality...
US-1,016,2616 System for binary translation version protection
The present disclosure is directed to a system for binary translation version protection. Activity occurring in a device that may potentially cause native code...
US-1,016,2496 Presentation of metadata and enhanced entertainment media content
Techniques are disclosed that involve providing enhanced user experiences involving the consumption and management of content. For instance, embodiments provide...
US-1,016,2405 Graphics processor power management contexts and sequential control loops
One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some...
US-1,016,2382 Apparatus, systems and methods to remove heat from a device
Methods, apparatus, systems are disclosed for using a movable heat sink to cool an electrical device during an ejection cycle of the electrical device from a...
US-1,015,9152 Development of the advanced component in cavity technology
Embodiments of the invention include a printed circuit board (PCB) assembly that includes advanced component in cavity (ACC) technology and methods of forming...
US-1,015,9060 Coordinated basic set (BSS) communication with different modulation coding scheme (MCS) per link
Methodologies are presented that provide better uplink and downlink data throughput for cell-edge stations (CE STAs) in wireless networks. In downlink, two or...
US-1,015,9016 Methods and devices for performing circuit-switched fallback
A communication circuit arrangement may include a control circuit configured to receive an initial call notification attempt in idle mode from a first network...
US-1,015,9002 Network management
Embodiments relate to network management of a wireless network in which inactive cells are selectively activated thereby changing the radio environment of a...
US-1,015,8914 Aggregated stress monitoring to guide user interaction
A system and method for real-time alteration of media content based on stress monitoring is disclosed. A computer system present a single media content item in...
US-1,015,8889 Replaying old packets for concealing video decoding errors and video decoding latency adjustment based on...
Systems, apparatus, articles, and methods are described below including operations for replaying old packets for concealing video decoding errors as well as...
US-1,015,8851 Techniques for improved graphics encoding
Techniques for improved graphics encoding are described. In one embodiment, for example, a device may include a processor circuit and a graphics encoding...
US-1,015,8833 High dynamic range imager enhancement technology
Imaging systems providing high resolution, low light images with significant dynamic range are disclosed. The improvements to photo imaging sensors providing...
US-1,015,8802 Trajectory planning for video stabilization
Trajectory planning is described for video stabilization. In one example, a sequence of video frames is received and low-pass filtered. If a subset of the...
US-1,015,8671 Reverse DRM geo-fencing of UAV method and apparatus
Apparatuses, methods and storage medium associated with reverse DRM geo-fencing are disclosed. In embodiments, an UAV may comprise sensors to provide sensor...
US-1,015,8585 Packet processing with reduced latency
Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue...
US-1,015,8582 Device-to-device communication for resource sharing
Embodiments of techniques and systems associated with device-to-device (D2D) resource sharing are described. In some embodiments, a D2D communication channel...
US-1,015,8578 Traffic management
One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to...
US-1,015,8519 Coordination of self-optimization operations in a self organizing network
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for coordinating a plurality of...
US-1,015,8512 Techniques to manage dwell times for pilot rotation
Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of...
US-1,015,8485 Double affine mapped S-box hardware accelerator
A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to...
US-1,015,8484 Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a...
US-1,015,8478 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-1,015,8473 Methods, apparatuses, and systems for transmitting hybrid automatic repeat request transmissions using channels...
Methods, systems, and storage media for providing and/or obtaining feedback for data transmissions in an unlicensed shared medium are described. In embodiments,...
US-1,015,8464 Mobile terminal devices, mobile processing circuits, and methods of processing signals
A mobile terminal device may include a receiver circuit and a processing circuit. The receiver circuit may be configured to receive a composite signal...
US-1,015,8451 Configurable constellation mapping to control spectral efficiency versus signal-to-noise ratio
Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and...
US-1,015,8406 Codebook for full-dimension multiple input multiple output communications
Various embodiments include an apparatus to be employed by an enhanced Node B (eNB), the apparatus comprising communication circuitry to receive, from a user...
US-1,015,8376 Techniques to accelerate lossless compression
An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a...
US-1,015,8362 Apparatus for providing shared reference device wherein an internal device is calibrated using reference device...
Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to...
US-1,015,8346 Pulse triggered flip flop
A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The...
US-1,015,8339 Capacitive compensation structures using partially meshed ground planes
Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example...
US-1,015,8065 Spin-transfer torque memory (STTM) devices having magnetic contacts
Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM)...
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