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Patent # Description
US-9,640,880 Cable connector
A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin...
US-9,640,646 Semiconductor device having group III-V material active region and graded gate dielectric
Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an...
US-9,640,622 Selective epitaxially grown III-V materials based devices
A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V...
US-9,640,537 Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and...
A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one...
US-9,639,490 Ring protocol for low latency interconnect switch
Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed...
US-9,639,134 Method and apparatus to provide telemetry data to a power controller of a processor
In an embodiment, a processor includes a plurality of cores including a first core. The first core includes a first plurality of accumulator logics, each...
US-9,639,133 Accurate power-on detector
Described is an apparatus which comprises: an input for providing a first voltage signal; a level translator, coupled to the input, to translate the first...
US-9,635,655 Enhancement to the buffer status report for coordinated uplink grant allocation in dual connectivity in an LTE...
Technology for efficiently splitting a bearer at the packet data convergence protocol (PDCP) layer for uplink (UL) data transfers in wireless networks where...
US-9,635,530 User equipment (UE) supporting packet-switched emergency calls over IP multimedia subsystem (IMS)
Embodiments of a mobile device, a User Equipment (UE), and method for supporting emergency calls on a packet-switched network are generally described herein. In...
US-9,634,124 Interlayer dielectric for non-planar transistors
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a...
US-9,633,983 Semiconductor chip stacking assemblies
Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second...
US-9,633,938 Hybrid pitch package with ultra high density interconnect capability
A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller...
US-9,633,835 Transistor fabrication technique including sacrificial protective layer for source/drain at contact location
Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The...
US-9,633,716 Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or...
Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted...
US-9,633,407 CPU/GPU synchronization mechanism
A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a...
US-9,633,374 System and methods for rebroadcasting of radio ads over other mediums
A method and system for specifying content of interest using a digital radio broadcast receiver is described. A digital radio broadcast signal includes an...
US-9,633,255 Substitution of handwritten text with a custom handwritten font
Systems, apparatuses and methods may provide font substitution based on a custom font. In one example, a custom handwritten font may be generated based on a...
US-9,633,230 Hardware assist for privilege access violation checks
Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the...
US-9,632,980 Apparatus and method of mask permute instructions
An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to...
US-9,632,907 Tracking deferred data packets in a debug trace architecture
A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order...
US-9,632,825 Method and apparatus for efficient scheduling for asymmetrical execution units
A method for performing instruction scheduling in an out-of-order microprocessor pipeline is disclosed. The method comprises selecting a first set of...
US-9,632,801 Banked memory access efficiency by a graphics processor
Conversion of an array of structures (AOS) to a structure of arrays (SOA) improves the efficiency of transfer from the AOS to the SOA. A similar technique can...
US-9,632,792 Coalescing adjacent gather/scatter operations
According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first...
US-9,632,790 Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed...
A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order...
US-9,631,065 Methods of forming wafer level underfill materials and structures formed thereby
Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming...
US-9,630,175 Self-aligned nanogap fabrication
Disclosed herein is a method comprising: depositing a second electrode of each of a plurality of electrode pairs onto a substrate, through an opening of one or...
US-9,629,145 Resource allocation techniques for device-to-device (D2D) communications
Resource allocation techniques for D2D communications are described. In one embodiment, for example, user equipment may comprise one or more radio frequency...
US-9,629,101 Adjustment of bluetooth (BT) golden reception range in the presence of long term evolution (LTE) interference
Described herein are methods, architectures and platforms for adjusting a reception range at which remote devices transmit to a Bluetooth receiver, by...
US-9,628,695 Method and system of lens shift correction for a camera array
A system, article, and method of lens shift correction for a camera array.
US-9,628,478 Technologies for secure storage and use of biometric authentication information
Generally, this disclosure describes technologies for securely storing and using biometric authentication information, such as biometric reference templates. In...
US-9,628,451 Power and cost efficient peripheral input
Systems and methods may provide for receiving, at a controller of a first device having a host processor, user input data and converting the user input data...
US-9,628,325 Method and system for recognizing radio link failures associated with HSUPA and HSDPA channels
A method and system for detecting radio link (RL) failures between a wireless transmit/receive unit (WTRU) and a Node-B are disclosed. When signaling radio...
US-9,628,305 Systems and methods to compensate for memory effects using enhanced memory polynomials
A system for mitigating non-linearity distortions from a memory effect is disclosed. The system includes an enhanced predistortion component, a power amplifier,...
US-9,628,277 Methods, systems and apparatus to self authorize platform code
Methods and apparatus are disclosed to self authorize platform code. A disclosed example apparatus to verify safety of a policy data structure (PDS) of a...
US-9,626,793 Variable depth compression
In accordance with some embodiments, the number of bits allocated to depth compression may be changed variably based on a number of considerations. As a result,...
US-9,626,531 Secure control of self-encrypting storage devices
Generally, this disclosure provides systems, devices, methods and computer readable media for secure control of access control enablement and activation on...
US-9,626,333 Scatter using index array and finite state machine
Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode...
US-9,626,299 Changing a hash function based on a conflict ratio associated with cache sets
Data and a memory address associated with the data may be received. A hash value of the memory address may be calculated by using a first hash function. The...
US-9,626,274 Instruction and logic for tracking access to monitored regions
A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a...
US-9,626,194 Thread livelock unit
Method, apparatus, and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at...
US-9,625,890 Coordinating control loops for temperature control
In one example a controller comprises logic, at least partially including hardware logic, configured to define a control relationship between a first control...
US-9,622,339 Routing design for high speed input/output links
Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer...
US-9,621,540 Secure provisioning of computing devices for enterprise connectivity
Technologies for securely provisioning a personal computing device for enterprise connectivity includes a trusted computing device for wirelessly communicating...
US-9,620,188 MTJ spin hall MRAM bit-cell and array
An apparatus is described having a select line and an interconnect with Spin Hall Effect (SHE) material. The interconnect is coupled to a write bit line. A...
US-9,619,859 Techniques for efficient GPU triangle list adjacency detection and handling
An apparatus may include a memory to store a set of triangle vertices in a triangle, a processor circuit coupled to the memory and a cache to cache a set of...
US-9,619,006 Router parking in power-efficient interconnect architectures
A method and apparatus for selectively parking routers used for routing traffic in mesh interconnects. Various router parking (RP) algorithms are disclosed,...
US-D783,603 Electronic device
US-9,615,483 Techniques and configurations associated with a package load assembly
Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package...
US-9,615,418 Segemented light guide panels in liquid crystal displays
An electronic device (e.g., computing device, all-in-one computing system, stand-alone display, etc.) having a liquid crystal display (LCD) panel, and a light...
US-9,615,395 Systems, methods, and devices for controlling transport of ratelessly coded messages
Systems, methods, and devices for controlling transport of ratelessly coded messages are disclosed herein. User equipment (UE) may be configured to receive a...
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