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Patent # Description
US-1,014,6570 Nested virtualization for virtual machine exits
Memory security technologies are described. An example processing device includes a processor core and a memory controller coupled to the processor core and a...
US-1,014,6548 Method for populating a source view data structure by using register template snapshots
A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using...
US-1,014,6544 Method and apparatus to process SHA-2 secure hashing algorithm
A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction...
US-1,014,6542 Hardware apparatus and methods for converting encoding formats
Methods and apparatuses relating to converting encoding formats are described. In one embodiment, a hardware processor includes a decode circuit to decode an...
US-1,014,6541 Processor to execute shift right merge instructions
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises...
US-1,014,6538 Suspendable load address tracking inside transactions
Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional...
US-1,014,6536 Method and apparatus for performing logical compare operations
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
US-1,014,6535 Systems, apparatuses, and methods for chained fused multiply add
Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single...
US-1,014,6533 Instruction and logic for detecting numeric accumulation error
A processor includes circuitry to decode at least one instruction and an execution unit. The decoded instruction may compute a floating point result. The...
US-1,014,6440 Apparatus, system and method for offloading collision check operations in a storage device
Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check...
US-1,014,6375 Feature characterization from infrared radiation
Systems, apparatuses, and/or methods to characterize a user feature. For example, and apparatus may include a pattern receiver to receive a feature infrared...
US-1,014,6322 Gesture pre-processing of video stream using a markered region
Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive...
US-1,014,6310 Haptic user interface control
Systems, apparatuses, and methods may include generating a three-dimensional model based on a two-dimensional image, determining one or more material...
US-1,014,6291 Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a...
US-1,014,6290 Platform communication protocol
A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the...
US-1,014,6287 Processor power monitoring and control with dynamic load balancing
Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of...
US-1,014,6286 Dynamically updating a power management policy of a processor
In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine,...
US-1,014,6283 Controlling power delivery to a processor via a bypass
In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear...
US-1,014,5942 Techniques for spatio-temporal compressed time of flight imaging
Various embodiments are generally directed to an apparatus, method, system, and/or other techniques to determine estimated ambient electromagnetic (EM)...
US-1,014,5694 Technologies for providing information to a user while traveling
Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a...
US-1,014,3421 System and method for user nudging via wearable devices
A method is described to facilitate behavioral nudging. The method includes receiving sensory data from one or more wearable devices, determining a context for...
US-1,014,3029 Device and method for recovering services from network rejections to wireless communication devices
A wireless communication device is described in one example comprising a first communication module circuitry to communicatively couple the wireless...
US-1,014,2999 Resource selection in device to device communication
A wireless communication device is configured to perform resource allocation of device-to-device (D2D) communication in a UE. Synchronization establishing...
US-1,014,2942 Apparatus, computer readable medium, and method for spatial reuse in a high efficiency wireless local-area network
Apparatus, computer readable medium, and method for generating and receiving signal fields in a high efficiency wireless local-area network (WLAN) are...
US-1,014,2931 Prioritized access in awake window
Devices and methods of for wireless communication in a directional multi-gigabit (DMG) band are generally described. A device can detect a starting point of an...
US-1,014,2894 Interworking/co-existence of integrated WLAN/3GPP RAT architectures with legacy WLAN/3GPP interworking solutions
An integrated WLAN/WWAN architecture is described, in which signaling used to control the integration of the WLAN/WWAN architecture is performed over the Radio...
US-1,014,2862 Wireless network location techniques
Improved wireless network location techniques are described. In one embodiment, for example, an apparatus may comprise circuitry and a communications management...
US-1,014,2771 Virtual sensor apparatus and method
Apparatuses, methods and storage medium associated with provision and receipt of virtual sensor service, are disclosed. In embodiments, an apparatus may...
US-1,014,2633 Flexible coding unit ordering and block sizing
A method for flexible encoding is described herein. The method includes selecting a largest coding unit size of a current frame based on a largest coding unit...
US-1,014,2553 Camera and light source synchronization for object tracking
Technologies for camera and light source synchronization include an imaging device to detect a current location of an object in a captured image generated by...
US-1,014,2533 Technologies for controlling user access to image sensors of a camera device
Technologies for managing access to image data streams generated by a plurality of image sensors of an image sensor array include a camera driver module. The...
US-1,014,2483 Technologies for dynamic audio communication adjustment
Technologies for adaptive audio communications include a telecommunications device configured to collect session data of a communication session that includes...
US-1,014,2237 Communication control method and system
A data flow control method and communication device operable to communicate using a first radio access technology (RAT) and a second RAT are described. In a...
US-1,014,2231 Technologies for network I/O access
Technologies for accelerating non-uniform network input/output accesses include a multi-home network interface controller (NIC) of a network computing device...
US-1,014,2101 Hardware enforced one-way cryptography
Embodiments of an invention for hardware enforced one-way cryptography are disclosed. In one embodiment, a processor includes a processor key location,...
US-1,014,2098 Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining
A processing system includes a processor to construct an input message comprising a plurality of padding bits and a hardware accelerator, communicatively...
US-1,014,2084 Full-duplex self-interference cancellation
This disclosure describes methods and devices related to self-interference cancellation. A device is disclosed comprising: at least one memory storing...
US-1,014,2064 Techniques and configurations associated with machine type communication in enhanced coverage mode
Embodiments of the present disclosure describe systems and methods for enhanced coverage machine type communication (MTC). Various embodiments may include...
US-1,014,2040 Apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature...
An apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal is provided. The in-phase signal and...
US-1,014,2007 Radio communication devices and methods for controlling a radio communication device
A device a radio communication device may be provided. The radio communication device may include: an antenna configured to operate in a plurality of operation...
US-1,014,1993 Modular antenna array beam forming
A radio communication device includes a plurality of antenna arrays each configured to generate a steerable antenna beam according to a respective beamforming...
US-1,014,1935 Programmable on-die termination timing in a multi-rank system
On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses...
US-1,014,1630 Antenna incorporated into device hinge and method
A method and apparatus for switching between two antenna elements in an electronic device having a hinge. A rotating element within the hinge has a coupling or...
US-1,014,1442 Semiconductor device having tipless epitaxial source/drain regions
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device...
US-1,014,1437 Extreme high mobility CMOS logic
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS...
US-1,014,1322 Metal floating gate composite 3D NAND memory devices and associated methods
A 3D NAND memory structure having improved process margin and enhanced performance is provided. Such a memory structure can include a control gate material and...
US-1,014,1311 Techniques for achieving multiple transistor fin dimensions on a single die
Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved...
US-1,014,1265 Bent-bridge semiconductive apparatus
A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of...
US-1,014,1241 Multi-chip self adjusting cooling solution
An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first passive heat exchanger disposed on...
US-1,014,1226 Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate...
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