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Patent # Description
US-1,013,6516 Microelectronic device attachment on a reverse microelectronic package
The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate...
US-1,013,6447 Signaling for inter-cell D2D discovery in an LTE network
Embodiments of an enhanced node B (eNB), user equipment (UE) and methods of signaling for proximity services and device-to-device (D2D) discovery in an LTE...
US-1,013,6368 Handover at spectrum release for licensed shared access
Embodiments of Evolved Node-B (eNBs), user equipment (UE) and methods for licensed shared access (LSA) handover are generally described herein. An eNB includes...
US-1,013,5954 Access dock device content on a remote client device wirelessly
Apparatuses, methods and storage medium associated with accessing dock device content on a remote client device wirelessly are disclosed herein. In embodiments,...
US-1,013,5828 Technologies for secure server access using a trusted license agent
Technologies for secure server access include a client computing device that loads a license agent into a secure enclave established by a processor of the...
US-1,013,5825 Protecting supervisor mode information
Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction...
US-1,013,5730 Methods, apparatuses, and systems for retrieving data from a wireless local area network (WLAN) access point
Methods, apparatuses, and systems are described related to retrieving data from a wireless local area network (WLAN) access point (AP). In embodiments, an...
US-1,013,5711 Technologies for sideband performance tracing of network traffic
Technologies for tracing network performance include a network computing device configured to receive a network packet from a source endpoint node, process the...
US-1,013,5708 Technologies for performance inspection at an endpoint node
Technologies for monitoring communication performance of a high performance computing (HPC) network include a performance probing engine of a source endpoint...
US-1,013,5622 Flexible provisioning of attestation keys in secure enclaves
A computing platform implements one or more secure enclaves including a first provisioning enclave to interface with a first provisioning service to obtain a...
US-1,013,5586 Reference signal enhancement for shared cell
In embodiments, apparatuses, methods, and storage media may be described for distinguishing, by a user equipment (UE), a reference signal (RS) transmitted by a...
US-1,013,5563 Triggering of an uplink pair of packets in a wireless local area network
Apparatuses, methods, and computer readable media for triggering of an uplink pair of packets in a wireless local area network. An apparatus is disclosed...
US-1,013,5530 Techniques for optical wireless communication
Optical wireless communication techniques are described and claimed. In one embodiment, the disclosure relates to method and apparatus to provide optical...
US-1,013,5515 Antenna beam training and tracking protocol for 60 GHz operation
A particular communications protocol is used for antenna training to accomplish directional communications in a wireless communications network. In some...
US-1,013,5494 Connection and synchronization with a device in a non-active state based on near field communication
Technologies for one-tap connection and synchronization with a device in a non-active state are disclosed. When a user brings a first device enabled for Near...
US-1,013,5481 Radio frequency shielding within a semiconductor package
Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and...
US-1,013,5463 Method and apparatus for accelerating canonical huffman encoding
In one embodiment, an apparatus comprises a memory; and a compression engine comprising circuitry, the compression engine to assign weights to a plurality of...
US-1,013,5461 Systems, methods, and apparatuses for decompression using hardware and software
Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming...
US-1,013,5240 Stacked switch circuit having shoot through current protection
An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an...
US-1,013,4809 Dual-layer dielectric in memory device
Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines...
US-1,013,4758 Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
US-1,013,4727 High breakdown voltage III-N depletion mode MOS capacitors
III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to...
US-1,013,4716 Multi-package integrated circuit assembly with through-mold via
A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first...
US-1,013,4690 Floating package stiffener
Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package...
US-1,013,4656 Package integrated synthetic jet device
Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling...
US-1,013,4471 Hybrid memory architectures
Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.
US-1,013,4468 Cross point memory control
The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL)...
US-1,013,4463 Reconfigurable clocking architecture
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit...
US-1,013,4360 Compressing the size of color lookup tables
By converting a first color space to a second color space, using a two-dimensional lookup table in said second color space, and converting from said second...
US-1,013,4314 Reducing power for 3D workloads
Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D...
US-1,013,4196 Mobile augmented reality system
Embodiments of the invention relate to systems, apparatuses and methods to provide image data, augmented with related data, to be displayed on a mobile...
US-1,013,4188 Body-centric mobile point-of-view augmented and virtual reality
Embodiments of a system and methods for displaying virtual or augmented reality are generally described herein. An image of a user may be captured using a...
US-1,013,4170 Stereoscopic rendering using vertix shader instancing
Various embodiments are generally directed to techniques to generate stereoscopic views of a scene for purposes of providing an illusion of depth to the scene....
US-1,013,4160 Anti-aliasing for graphics hardware
Visibility may be analytically resolved rather than using point-sampling, thereby entirely avoiding geometric aliasing and the need to store multiple samples...
US-1,013,4115 Progressive multisample anti-aliasing
One embodiment provides for a general-purpose graphics processor comprising a fragment processing unit configured to generate pixel color data in a graphics...
US-1,013,4101 Using cost estimation to improve performance of tile rendering for image processing
An analysis of the cost of processing tiles may be used to decide how to process the tiles. In one case two tiles may be merged. In another case a culling...
US-1,013,3982 Complex NFA state matching method that matches input symbols against character classes (CCLS), and compares...
Disclosed is a method and system for matching a complex NFA state comprising a spinner followed by a character class sequence which may be represented by the...
US-1,013,3697 Computer architecture to provide flexibility and/or scalability
Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot...
US-1,013,3674 System and method for one step address translation of graphics addresses in virtualization
A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual...
US-1,013,3670 Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric
In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the...
US-1,013,3669 Sequential data writes to increase invalid to modified protocol occurrences in a computing system
An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache...
US-1,013,3668 Technologies for providing cross data storage device communications
Technologies for providing cross data storage device communication include a compute device to transmit, with a processor, a move request to a first data...
US-1,013,3620 Detecting errors in register renaming by comparing value representing complete error free set of identifiers...
A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time,...
US-1,013,3601 Memory management
System and techniques for memory management are described herein. A request for an adjusted process-value for a process may be received. Here, the adjusted...
US-1,013,3597 Intelligent GPU scheduling in a virtualization environment
Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a...
US-1,013,3582 Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor
A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction...
US-1,013,3577 Vector mask driven clock gating for power efficiency of a processor
A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform...
US-1,013,3570 Processors, methods, systems, and instructions to select and consolidate active data elements in a register...
A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a...
US-1,013,3482 Adaptive virtual keyboard for handheld device
In various embodiments, the size, shape, and arrangement of keys on a virtual keyboard may be determined based on touchscreen contacts made by the user....
US-1,013,3396 Virtual input device using second touch-enabled display
An example system for generating hardware device input includes a gesture detector to detect an input device trigger from one of two coupled touch-enabled...
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