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Patent # Description
US-1,010,4636 Location information for voice over WLAN emergency calling
Briefly, in accordance with one or more embodiments, user equipment (UE) comprises processing circuitry to connect to a network via an untrusted wireless local...
US-1,010,4176 Remote management for a computing device
Examples are disclosed for remote management of a computing device. In some examples, a secure communication link may be established between a network...
US-1,010,4145 System and method for caching data
A method of obtaining radio content from a remote electronic device for a user electronic device includes transmitting a request for radio media content to a...
US-1,010,4122 Verified sensor data processing
Sensor data may be filtered in a secure environment. The filtering may limit distribution of the sensor data. Filtering may modify the sensor data, for example,...
US-1,010,3889 Securely exchanging vehicular sensor information
Technologies for securely exchanging sensor information include an in-vehicle computing system of a vehicle to establish a trusted execution environment and a...
US-1,010,3877 SMS4 acceleration processors having round constant generation
A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an...
US-1,010,3873 Power side-channel attack resistant advanced encryption standard accelerator processor
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a...
US-1,010,3872 Securing audio communications
Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is...
US-1,010,3847 Methods apparatus of eNB and UE for MTC with narrowband deployment
Systems, apparatus, user equipment (UE), evolved node B(eNB), and methods are described for machine-type communications (MTC) with narrowband deployment...
US-1,010,3797 Quasi co-location and PDSCH resource element mapping signaling for network assisted interference mitigation
Embodiments of the present disclosure describe systems and methods for mitigating interference in wireless networks. Various embodiments may include signaling...
US-1,010,3796 Apparatus, system and method of selectively responding to wireless transmissions
Some demonstrative embodiments include apparatuses, systems and/or methods of selectively responding to wireless communication transmissions. For example, an...
US-1,010,3792 Apparatus, system and method of communicating a multiple-input-multiple-output (MIMO) transmission
For example, a wireless station may be configured to generate a plurality of time-domain streams in a time domain, the plurality of time-domain streams...
US-1,010,3761 Local oscillator signal generation using opportunistic synthesizer to clock digital synthesis
Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity...
US-1,010,3758 Trajectory modification technique for polar transmitter
This application discussed trajectory modification techniques for polar transmission architectures. In an example, a method can include receiving a first...
US-1,010,3613 Mirror driving device
A mirror drive device is provided whereby conduction faults due to short-circuiting can be eliminated. A mirror drive device 1A is provided with a fixed frame,...
US-1,010,3585 Regulated load modulation circuit and method for producing regulated load modulation signaling
A load modulation circuit includes a resonator circuit configured to resonate based on a received charging power and produce a resonance output signal based...
US-1,010,3542 Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection
Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may...
US-1,010,3434 Millimeter-wave high-gain steerable reflect array-feeding array antenna in a wireless local area networks
A reflect array-feeding array (RA-FA) antenna is disclosed. The RA-FA antenna comprising: a reflect array base comprising a plurality of reflecting elements...
US-1,010,3263 Strained channel region transistors employing source and drain stressors and systems including the same
Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source...
US-1,010,3105 High density organic bridge device and method
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
US-1,010,3103 Bridge interconnection with layered interconnect structures
Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in...
US-1,010,3088 Integrated antenna for direct chip attach connectivity module package structures
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a...
US-1,010,3054 Coupled vias for channel cross-talk reduction
Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall...
US-1,010,3037 Flexible microelectronic systems and methods of fabricating the same
Microelectronic systems encapsulated in a stretchable/flexible material, which is skin/bio-compatible and able to withstand environmental conditions. In one...
US-1,010,2903 Write process for a non volatile memory device
An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non...
US-1,010,2892 RAM-based shift register with embedded addressing
Unlike prior RAM-based shift register circuits, the presently-disclosed shift register circuit does not require control circuits to generate write and read...
US-1,010,2891 Double-polarity memory read
Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves...
US-1,010,2888 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction...
US-1,010,2886 Techniques for probabilistic dynamic random access memory row repair
Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum...
US-1,010,2835 Sensor driven enhanced visualization and audio effects
Systems and methods may be used to provide effects corresponding to movement of instrument objects or other objects. A method may include receiving sensor data...
US-1,010,2609 Low granularity coarse depth test efficiency enhancement
Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4.times.4 blocks of pixels using...
US-1,010,2606 Transmission of data based on a configuration database
In one example, a system for transmitting data comprises a processor to load a configuration database into memory accessible by the graphics processing unit....
US-1,010,2604 Data distribution fabric in scalable GPUs
In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data...
US-1,010,2419 Progressive radar assisted facial recognition
System and techniques for progressive radar assisted facial recognition are described herein. An image may be obtained from a camera of the security device. A...
US-1,010,2380 Method and apparatus to provide secure application execution
A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an...
US-1,010,2370 Techniques to enable scalable cryptographically protected memory using on-chip memory
Techniques to enable scalable cryptographically protected memory using on-chip memory are described. In one embodiment, an apparatus may comprise a processor...
US-1,010,2215 Apparatus for hardware implementation of lossless data compression
A processor includes a memory hierarchy, buffer, and a compression module. The compression module includes logic to evaluate a stream of data to be compressed...
US-1,010,2157 Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and...
A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in...
US-1,010,2149 Replacement policies for a hybrid hierarchical cache
A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time,...
US-1,010,2141 System and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
US-1,010,2134 Instruction and logic for run-time evaluation of multiple prefetchers
A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The...
US-1,010,2129 Minimizing snoop traffic locally and across cores on a chip multi-core fabric
A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality...
US-1,010,2126 Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one...
US-1,010,2124 High bandwidth full-block write commands
A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high...
US-1,010,2123 Hybrid hardware and software implementation of transactional memory access
Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a...
US-1,010,2089 Input/output (I/O) device configuration signature
A method for building a configuration signature for an input/output (I/O) device is described herein. The configuration signature is built based on descriptors...
US-1,010,2035 Techniques for computing resource discovery and management in a data center
Examples are described for computing resource discovery and management for a system of configurable computing resources that may include disaggregate physical...
US-1,010,2000 Apparatus and method for non-serializing split locks
An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a...
US-1,010,1999 Memory address collision detection of ordered parallel threads with bloom filters
A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store...
US-1,010,1955 Binding for audio/video streaming in a topology of devices
Resources may be managed in a topology for audio/video streaming. The topology includes audio/video sources and sinks and intervening branch devices. Messages...
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